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| author | Adrian Hunter <adrian.hunter@intel.com> | 2021-12-02 11:50:25 +0200 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2022-01-23 20:37:46 +0100 |
| commit | 9dd94df75b30eca03ed2151dd5bbc152a6f19abf (patch) | |
| tree | b74521da67d1629fafe08482bfe7aed312088ffa /tools/arch | |
| parent | 4810dd2c943edd98cd41a12b96745b16b1d6b4f5 (diff) | |
| download | lwn-9dd94df75b30eca03ed2151dd5bbc152a6f19abf.tar.gz lwn-9dd94df75b30eca03ed2151dd5bbc152a6f19abf.zip | |
x86/insn: Add AMX instructions to the x86 instruction decoder
The x86 instruction decoder is used for both kernel instructions and
user space instructions (e.g. uprobes, perf tools Intel PT), so it is
good to update it with new instructions.
Add AMX instructions to the x86 instruction decoder.
Reference:
Intel Architecture Instruction Set Extensions and Future Features
Programming Reference
May 2021
Document Number: 319433-044
Example using perf tools' x86 instruction decoder test:
$ INSN='ldtilecfg\|sttilecfg\|tdpbf16ps\|tdpbssd\|'
$ INSN+='tdpbsud\|tdpbusd\|'tdpbuud\|tileloadd\|'
$ INSN+='tileloaddt1\|tilerelease\|tilestored\|tilezero'
$ perf test -v "x86 instruction decoder" |& grep -i $INSN
Decoded ok: c4 e2 78 49 04 c8 ldtilecfg (%rax,%rcx,8)
Decoded ok: c4 c2 78 49 04 c8 ldtilecfg (%r8,%rcx,8)
Decoded ok: c4 e2 79 49 04 c8 sttilecfg (%rax,%rcx,8)
Decoded ok: c4 c2 79 49 04 c8 sttilecfg (%r8,%rcx,8)
Decoded ok: c4 e2 7a 5c d1 tdpbf16ps %tmm0,%tmm1,%tmm2
Decoded ok: c4 e2 7b 5e d1 tdpbssd %tmm0,%tmm1,%tmm2
Decoded ok: c4 e2 7a 5e d1 tdpbsud %tmm0,%tmm1,%tmm2
Decoded ok: c4 e2 79 5e d1 tdpbusd %tmm0,%tmm1,%tmm2
Decoded ok: c4 e2 78 5e d1 tdpbuud %tmm0,%tmm1,%tmm2
Decoded ok: c4 e2 7b 4b 0c c8 tileloadd (%rax,%rcx,8),%tmm1
Decoded ok: c4 c2 7b 4b 14 c8 tileloadd (%r8,%rcx,8),%tmm2
Decoded ok: c4 e2 79 4b 0c c8 tileloaddt1 (%rax,%rcx,8),%tmm1
Decoded ok: c4 c2 79 4b 14 c8 tileloaddt1 (%r8,%rcx,8),%tmm2
Decoded ok: c4 e2 78 49 c0 tilerelease
Decoded ok: c4 e2 7a 4b 0c c8 tilestored %tmm1,(%rax,%rcx,8)
Decoded ok: c4 c2 7a 4b 14 c8 tilestored %tmm2,(%r8,%rcx,8)
Decoded ok: c4 e2 7b 49 c0 tilezero %tmm0
Decoded ok: c4 e2 7b 49 f8 tilezero %tmm7
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Acked-by: Masami Hiramatsu <mhiramat@kernel.org>
Link: https://lore.kernel.org/r/20211202095029.2165714-3-adrian.hunter@intel.com
Diffstat (limited to 'tools/arch')
| -rw-r--r-- | tools/arch/x86/lib/x86-opcode-map.txt | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/tools/arch/x86/lib/x86-opcode-map.txt b/tools/arch/x86/lib/x86-opcode-map.txt index ec31f5b60323..b2cc6c04cbfe 100644 --- a/tools/arch/x86/lib/x86-opcode-map.txt +++ b/tools/arch/x86/lib/x86-opcode-map.txt @@ -690,7 +690,10 @@ AVXcode: 2 45: vpsrlvd/q Vx,Hx,Wx (66),(v) 46: vpsravd Vx,Hx,Wx (66),(v) | vpsravd/q Vx,Hx,Wx (66),(evo) 47: vpsllvd/q Vx,Hx,Wx (66),(v) -# Skip 0x48-0x4b +# Skip 0x48 +49: TILERELEASE (v1),(000),(11B) | LDTILECFG Mtc (v1)(000) | STTILECFG Mtc (66),(v1),(000) | TILEZERO Vt (F2),(v1),(11B) +# Skip 0x4a +4b: TILELOADD Vt,Wsm (F2),(v1) | TILELOADDT1 Vt,Wsm (66),(v1) | TILESTORED Wsm,Vt (F3),(v) 4c: vrcp14ps/d Vpd,Wpd (66),(ev) 4d: vrcp14ss/d Vsd,Hpd,Wsd (66),(ev) 4e: vrsqrt14ps/d Vpd,Wpd (66),(ev) @@ -705,7 +708,10 @@ AVXcode: 2 59: vpbroadcastq Vx,Wx (66),(v) | vbroadcasti32x2 Vx,Wx (66),(evo) 5a: vbroadcasti128 Vqq,Mdq (66),(v) | vbroadcasti32x4/64x2 Vx,Wx (66),(evo) 5b: vbroadcasti32x8/64x4 Vqq,Mdq (66),(ev) -# Skip 0x5c-0x61 +5c: TDPBF16PS Vt,Wt,Ht (F3),(v1) +# Skip 0x5d +5e: TDPBSSD Vt,Wt,Ht (F2),(v1) | TDPBSUD Vt,Wt,Ht (F3),(v1) | TDPBUSD Vt,Wt,Ht (66),(v1) | TDPBUUD Vt,Wt,Ht (v1) +# Skip 0x5f-0x61 62: vpexpandb/w Vx,Wx (66),(ev) 63: vpcompressb/w Wx,Vx (66),(ev) 64: vpblendmd/q Vx,Hx,Wx (66),(ev) |