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| author | Pardha Saradhi K <pardha.saradhi.kesapragada@intel.com> | 2016-11-03 17:07:16 +0530 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2016-11-03 11:14:22 -0600 |
| commit | a26a3f53e3d2bfeb666ca31b5f86c65a1816eb89 (patch) | |
| tree | 16c2078a2f3aeed82afaf3bddd50e9a7122fc756 /sound/soc/intel/skylake/skl.h | |
| parent | 41b7523f192bdf3804e3e18a61f91244e4a0cb25 (diff) | |
| download | lwn-a26a3f53e3d2bfeb666ca31b5f86c65a1816eb89.tar.gz lwn-a26a3f53e3d2bfeb666ca31b5f86c65a1816eb89.zip | |
ASoC: Intel: Skylake: Add support for programming D0i3C
To set the controller in D0i3 mode, the driver needs to set D0i3C
register after DSP is quiesced. Since the D0iX entry/exit is done by IPC,
add this as callback so that it can be invoked from IPC module.
Signed-off-by: Pardha Saradhi K <pardha.saradhi.kesapragada@intel.com>
Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/intel/skylake/skl.h')
| -rw-r--r-- | sound/soc/intel/skylake/skl.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/sound/soc/intel/skylake/skl.h b/sound/soc/intel/skylake/skl.h index 5d4fbb094c48..88ba54ba5f72 100644 --- a/sound/soc/intel/skylake/skl.h +++ b/sound/soc/intel/skylake/skl.h @@ -52,6 +52,9 @@ #define AZX_PGCTL_LSRMD_MASK (1 << 4) #define AZX_PCIREG_CGCTL 0x48 #define AZX_CGCTL_MISCBDCGE_MASK (1 << 6) +/* D0I3C Register fields */ +#define AZX_REG_VS_D0I3C_CIP 0x1 /* Command in progress */ +#define AZX_REG_VS_D0I3C_I3 0x4 /* D0i3 enable */ struct skl_dsp_resource { u32 max_mcps; @@ -125,4 +128,6 @@ int skl_suspend_dsp(struct skl *skl); int skl_resume_dsp(struct skl *skl); void skl_cleanup_resources(struct skl *skl); const struct skl_dsp_ops *skl_get_dsp_ops(int pci_id); +void skl_update_d0i3c(struct device *dev, bool enable); + #endif /* __SOUND_SOC_SKL_H */ |