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authorKevin Groeneveld <kgroeneveld@lenbrook.com>2023-03-18 18:21:32 -0400
committerMark Brown <broonie@kernel.org>2023-04-04 12:46:54 +0100
commit87c614175bbf28d3fd076dc2d166bac759e41427 (patch)
tree65e89e9fff3b126f5417330d93778a6c0fcbadb0 /scripts/generate_rust_analyzer.py
parentc2912d42e86e494935722669e4d9eade69649072 (diff)
downloadlwn-87c614175bbf28d3fd076dc2d166bac759e41427.tar.gz
lwn-87c614175bbf28d3fd076dc2d166bac759e41427.zip
spi: spi-imx: fix MX51_ECSPI_* macros when cs > 3
When using gpio based chip select the cs value can go outside the range 0 – 3. The various MX51_ECSPI_* macros did not take this into consideration resulting in possible corruption of the configuration. For example for any cs value over 3 the SCLKPHA bits would not be set and other values in the register possibly corrupted. One way to fix this is to just mask the cs bits to 2 bits. This still allows all 4 native chip selects to work as well as gpio chip selects (which can use any of the 4 chip select configurations). Signed-off-by: Kevin Groeneveld <kgroeneveld@lenbrook.com> Link: https://lore.kernel.org/r/20230318222132.3373-1-kgroeneveld@lenbrook.com Signed-off-by: Mark Brown <broonie@kernel.org>
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