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authorMengdong Lin <mengdong.lin@intel.com>2014-07-03 17:02:23 +0800
committerJiri Slaby <jslaby@suse.cz>2014-11-05 10:03:19 +0100
commit7fccdb578ab6a71fc23690f772d37e7f0050a6bf (patch)
treeccdd21bda2b6a9b6f36a1b33c5339cb692efa6a0 /net
parente48c442a046d006ff87cd67a686a27a5f64dedbb (diff)
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ALSA: hda - restore BCLK M/N value as per CDCLK for HSW/BDW display HDA controller
commit e4d9e513dedb5ac4e166c1053314fa935ddecc8c upstream. For HSW/BDW display HD-A controller, hda_set_bclk() is defined to set BCLK by programming the M/N values as per the core display clock (CDCLK) queried from i915 display driver. And the audio driver will also set BCLK in azx_first_init() since the display driver can turn off the shared power in boot phase if only eDP is connected and M/N values will be lost and must be reprogrammed. Signed-off-by: Mengdong Lin <mengdong.lin@intel.com> Cc: <stable@vger.kernel.org> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jiri Slaby <jslaby@suse.cz>
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