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authorZhenyu Wang <zhenyuw@linux.intel.com>2009-09-02 10:57:52 +0800
committerGreg Kroah-Hartman <gregkh@suse.de>2009-10-05 09:32:11 -0700
commit522bb748440e5765e6f73b417544f821e27940a9 (patch)
treeb789ee5b0ff528f8773076b94febe4b6fd2817d0 /init
parent867d008ba440f7df63996722dc0f958b849291fb (diff)
downloadlwn-522bb748440e5765e6f73b417544f821e27940a9.tar.gz
lwn-522bb748440e5765e6f73b417544f821e27940a9.zip
drm/i915: fix tiling on IGDNG
commit 553bd149bb2de7848b2b84642876f27202421368 upstream. It seems that on IGDNG the same swizzling setup always applys. And front buffer tiling needs to set address swizzle in display arb control too. Fix plane tricle feed setting in v1 which should be disable bit, and always setup address swizzle to let hardware care for buffer tiling in all cases. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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