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author | Vladimir Oltean <vladimir.oltean@nxp.com> | 2020-07-05 19:16:21 +0300 |
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committer | David S. Miller <davem@davemloft.net> | 2020-07-05 15:25:58 -0700 |
commit | 3f2628d62dec9505d5f19044e5f0401989a6b796 (patch) | |
tree | f371cec2198dc6df3c41686e04445a2771aa5592 /include | |
parent | e1f04670440442b6218b391b5f822819fb3b8c6f (diff) | |
download | lwn-3f2628d62dec9505d5f19044e5f0401989a6b796.tar.gz lwn-3f2628d62dec9505d5f19044e5f0401989a6b796.zip |
net: dsa: felix: clarify the intention of writes to MII_BMCR
The driver appears to write to BMCR_SPEED and BMCR_DUPLEX, fields which
are read-only, since they are actually configured through the
vendor-specific IF_MODE (0x14) register.
But the reason we're writing back the read-only values of MII_BMCR is to
alter these writable fields:
BMCR_RESET
BMCR_LOOPBACK
BMCR_ANENABLE
BMCR_PDOWN
BMCR_ISOLATE
BMCR_ANRESTART
In particular, the only field which is really relevant to this driver is
BMCR_ANENABLE. Clarify that intention by spelling it out, using
phy_set_bits and phy_clear_bits.
The driver also made a few writes to BMCR_RESET and BMCR_ANRESTART which
are unnecessary and may temporarily disrupt the link to the PHY. Remove
them.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions