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| author | Esben Haabendal <esben@geanix.com> | 2019-05-23 14:02:20 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2019-05-23 09:33:57 -0700 |
| commit | 1bd33bf0fe6d3012410db0302187199871b510a0 (patch) | |
| tree | 1a5e9f58c4d08510a24af48a51aa4174974d0c57 /include/linux/platform_data/xilinx-ll-temac.h | |
| parent | ddc0bf34f9ee202315f8c844bcbdede4e3821f12 (diff) | |
| download | lwn-1bd33bf0fe6d3012410db0302187199871b510a0.tar.gz lwn-1bd33bf0fe6d3012410db0302187199871b510a0.zip | |
net: ll_temac: Prepare indirect register access for multicast support
With .ndo_set_rx_mode/temac_set_multicast_list() being called in atomic
context (holding addr_list_lock), and temac_set_multicast_list() needing
to access temac indirect registers, the mutex used to synchronize indirect
register is a no-no.
Replace it with a spinlock, and avoid sleeping in
temac_indirect_busywait().
To avoid excessive holding of the lock, which is now a spinlock, the
temac_device_reset() function is changed to only hold the lock for short
periods. With timeouts, it could be holding the spinlock for more than
2 seconds.
Signed-off-by: Esben Haabendal <esben@geanix.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/linux/platform_data/xilinx-ll-temac.h')
| -rw-r--r-- | include/linux/platform_data/xilinx-ll-temac.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/linux/platform_data/xilinx-ll-temac.h b/include/linux/platform_data/xilinx-ll-temac.h index 368530f98176..f4a68136afa6 100644 --- a/include/linux/platform_data/xilinx-ll-temac.h +++ b/include/linux/platform_data/xilinx-ll-temac.h @@ -4,6 +4,7 @@ #include <linux/if_ether.h> #include <linux/phy.h> +#include <linux/spinlock.h> struct ll_temac_platform_data { bool txcsum; /* Enable/disable TX checksum */ @@ -21,7 +22,7 @@ struct ll_temac_platform_data { * TEMAC IP block, the same mutex should be passed here, as * they share the same DCR bus bridge. */ - struct mutex *indirect_mutex; + spinlock_t *indirect_lock; /* DMA channel control setup */ u8 tx_irq_timeout; /* TX Interrupt Delay Time-out */ u8 tx_irq_count; /* TX Interrupt Coalescing Threshold Count */ |