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author | Bjorn Helgaas <bhelgaas@google.com> | 2018-04-04 13:27:40 -0500 |
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committer | Bjorn Helgaas <helgaas@kernel.org> | 2018-04-04 13:27:40 -0500 |
commit | 315271b0ff1976e8c4a1c2620cef39047a003390 (patch) | |
tree | 2738169a39129e8a08d74330c220104626a338bd /include/linux/pci.h | |
parent | db7a726ea8a26ae1e418f9e08845d64cbc079480 (diff) | |
parent | 170648fda93729f05d0758c76b8cd9170408471b (diff) | |
download | lwn-315271b0ff1976e8c4a1c2620cef39047a003390.tar.gz lwn-315271b0ff1976e8c4a1c2620cef39047a003390.zip |
Merge branch 'pci/enumeration'
- add decoding for 16 GT/s link speed (Jay Fang)
- add interfaces to get max link speed and width (Tal Gilboa)
- add pcie_bandwidth_capable() to compute max supported link bandwidth
(Tal Gilboa)
- add pcie_bandwidth_available() to compute bandwidth available to device
(Tal Gilboa)
- add pcie_print_link_status() to log link speed and whether it's limited
(Tal Gilboa)
- use PCI core interfaces to report when device performance may be
limited by its slot instead of doing it in each driver (Tal Gilboa)
* pci/enumeration:
fm10k: Report PCIe link properties with pcie_print_link_status()
net/mlx5e: Use pcie_bandwidth_available() to compute bandwidth
net/mlx5: Report PCIe link properties with pcie_print_link_status()
net/mlx4_core: Report PCIe link properties with pcie_print_link_status()
PCI: Add pcie_print_link_status() to log link speed and whether it's limited
PCI: Add pcie_bandwidth_available() to compute bandwidth available to device
PCI: Add pcie_bandwidth_capable() to compute max supported link bandwidth
PCI: Add pcie_get_width_cap() to find max supported link width
PCI: Add pcie_get_speed_cap() to find max supported link speed
PCI: Add decoding for 16 GT/s link speed
Diffstat (limited to 'include/linux/pci.h')
-rw-r--r-- | include/linux/pci.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/linux/pci.h b/include/linux/pci.h index 24e15510a946..926a8cb5d6d4 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -256,6 +256,7 @@ enum pci_bus_speed { PCIE_SPEED_2_5GT = 0x14, PCIE_SPEED_5_0GT = 0x15, PCIE_SPEED_8_0GT = 0x16, + PCIE_SPEED_16_0GT = 0x17, PCI_SPEED_UNKNOWN = 0xff, }; @@ -1077,6 +1078,10 @@ int pcie_get_mps(struct pci_dev *dev); int pcie_set_mps(struct pci_dev *dev, int mps); int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, enum pcie_link_width *width); +u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, + enum pci_bus_speed *speed, + enum pcie_link_width *width); +void pcie_print_link_status(struct pci_dev *dev); void pcie_flr(struct pci_dev *dev); int __pci_reset_function_locked(struct pci_dev *dev); int pci_reset_function(struct pci_dev *dev); |