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| author | Lu Baolu <baolu.lu@linux.intel.com> | 2021-01-15 08:42:02 +0800 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2021-01-28 11:33:35 +0100 |
| commit | a8ce9ebbecdfda3322bbcece6b3b25888217f8e3 (patch) | |
| tree | a869157ecd488fee69c6abd4a07087d0b7f8367e /include/linux/intel-iommu.h | |
| parent | f2dd871799ba5d80f95f9bdbc0e60d390e1bcd22 (diff) | |
| download | lwn-a8ce9ebbecdfda3322bbcece6b3b25888217f8e3.tar.gz lwn-a8ce9ebbecdfda3322bbcece6b3b25888217f8e3.zip | |
iommu/vt-d: Preset Access/Dirty bits for IOVA over FL
The Access/Dirty bits in the first level page table entry will be set
whenever a page table entry was used for address translation or write
permission was successfully translated. This is always true when using
the first-level page table for kernel IOVA. Instead of wasting hardware
cycles to update the certain bits, it's better to set them up at the
beginning.
Suggested-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20210115004202.953965-1-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'include/linux/intel-iommu.h')
| -rw-r--r-- | include/linux/intel-iommu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h index 09c6a0bf3892..ecb35fdff03e 100644 --- a/include/linux/intel-iommu.h +++ b/include/linux/intel-iommu.h @@ -42,6 +42,8 @@ #define DMA_FL_PTE_PRESENT BIT_ULL(0) #define DMA_FL_PTE_US BIT_ULL(2) +#define DMA_FL_PTE_ACCESS BIT_ULL(5) +#define DMA_FL_PTE_DIRTY BIT_ULL(6) #define DMA_FL_PTE_XD BIT_ULL(63) #define ADDR_WIDTH_5LEVEL (57) |