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| author | Haojian Zhuang <haojian.zhuang@linaro.org> | 2013-06-08 22:47:18 +0800 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2013-06-15 20:23:49 -0700 |
| commit | d57dfe7508af2b528e26d84792edec1e7d919682 (patch) | |
| tree | f3be7ce2e20cdf9fad2528b4a1972e29df20a662 /include/linux/clk-provider.h | |
| parent | ba492e900704ba00d43c7af9d94b00da4df52587 (diff) | |
| download | lwn-d57dfe7508af2b528e26d84792edec1e7d919682.tar.gz lwn-d57dfe7508af2b528e26d84792edec1e7d919682.zip | |
clk: divider: add CLK_DIVIDER_HIWORD_MASK flag
In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the
paradigm of reading-changing-writing the register contents.
Instead they use a hiword mask to indicate the changed bits.
When b01 should be set as setting divider, it also needs to indicate
the change by setting hiword mask (b11 << 16).
The patch adds divider flag for this usage.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'include/linux/clk-provider.h')
| -rw-r--r-- | include/linux/clk-provider.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 37ad97961e5a..d77f1267f419 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -257,6 +257,10 @@ struct clk_div_table { * Some hardware implementations gracefully handle this case and allow a * zero divisor by not modifying their input clock * (divide by one / bypass). + * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit + * of this register, and mask of divider bits are in higher 16-bit of this + * register. While setting the divider bits, higher 16-bit should also be + * updated to indicate changing divider bits. */ struct clk_divider { struct clk_hw hw; @@ -271,6 +275,7 @@ struct clk_divider { #define CLK_DIVIDER_ONE_BASED BIT(0) #define CLK_DIVIDER_POWER_OF_TWO BIT(1) #define CLK_DIVIDER_ALLOW_ZERO BIT(2) +#define CLK_DIVIDER_HIWORD_MASK BIT(3) extern const struct clk_ops clk_divider_ops; struct clk *clk_register_divider(struct device *dev, const char *name, |