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author | Stephen Boyd <sboyd@codeaurora.org> | 2016-04-15 16:02:46 -0700 |
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committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-04-15 16:02:46 -0700 |
commit | 75ff88888093eddca478a8fa1b77b30edb4fa8be (patch) | |
tree | 97990ff554f2e37084fa69a8fee891c13eb287be /include/dt-bindings | |
parent | c02b73c943d723511abecde7909d0818638d1bc2 (diff) | |
parent | 33b8ac917a8f7a22fa3d779f875646201d0097a0 (diff) | |
download | lwn-75ff88888093eddca478a8fa1b77b30edb4fa8be.tar.gz lwn-75ff88888093eddca478a8fa1b77b30edb4fa8be.zip |
Merge branch 'clk-artpec6' into clk-next
* clk-artpec6:
clk: add artpec-6 clock controller
clk: add device tree binding for Artpec-6 clock controller
Diffstat (limited to 'include/dt-bindings')
-rw-r--r-- | include/dt-bindings/clock/axis,artpec6-clkctrl.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/axis,artpec6-clkctrl.h b/include/dt-bindings/clock/axis,artpec6-clkctrl.h new file mode 100644 index 000000000000..f9f04dccc996 --- /dev/null +++ b/include/dt-bindings/clock/axis,artpec6-clkctrl.h @@ -0,0 +1,38 @@ +/* + * ARTPEC-6 clock controller indexes + * + * Copyright 2016 Axis Comunications AB. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H +#define DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H + +#define ARTPEC6_CLK_CPU 0 +#define ARTPEC6_CLK_CPU_PERIPH 1 +#define ARTPEC6_CLK_NAND_CLKA 2 +#define ARTPEC6_CLK_NAND_CLKB 3 +#define ARTPEC6_CLK_ETH_ACLK 4 +#define ARTPEC6_CLK_DMA_ACLK 5 +#define ARTPEC6_CLK_PTP_REF 6 +#define ARTPEC6_CLK_SD_PCLK 7 +#define ARTPEC6_CLK_SD_IMCLK 8 +#define ARTPEC6_CLK_I2S_HST 9 +#define ARTPEC6_CLK_I2S0_CLK 10 +#define ARTPEC6_CLK_I2S1_CLK 11 +#define ARTPEC6_CLK_UART_PCLK 12 +#define ARTPEC6_CLK_UART_REFCLK 13 +#define ARTPEC6_CLK_I2C 14 +#define ARTPEC6_CLK_SPI_PCLK 15 +#define ARTPEC6_CLK_SPI_SSPCLK 16 +#define ARTPEC6_CLK_SYS_TIMER 17 +#define ARTPEC6_CLK_FRACDIV_IN 18 +#define ARTPEC6_CLK_DBG_PCLK 19 + +/* This must be the highest clock index plus one. */ +#define ARTPEC6_CLK_NUMCLOCKS 20 + +#endif |