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| author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2019-05-28 11:27:29 +0300 |
|---|---|---|
| committer | Andrzej Hajda <a.hajda@samsung.com> | 2019-05-31 15:41:19 +0200 |
| commit | ca342386a9b3a47b3ed30c9a89e74c9ca6152cc6 (patch) | |
| tree | 7f5db6cee1eeaa0eca82cc832bda1ebfff1e4735 /drivers | |
| parent | ab947eb65a3191a0bc24ce18e226b2eae1e395ee (diff) | |
| download | lwn-ca342386a9b3a47b3ed30c9a89e74c9ca6152cc6.tar.gz lwn-ca342386a9b3a47b3ed30c9a89e74c9ca6152cc6.zip | |
drm/bridge: tc358767: cleanup aux_link_setup
The driver sets up AUX link at probe time, but, for some reason, also
sets the main link's number of lanes using tc->link.base.num_lanes. This
is not needed nor correct, as the number of lanes has not been decided
yet. The number of lanes will be set later during main link setup.
Modify aux_link_setup so that it does not use tc->link, and thus makes
aux setup independent of the link probing.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190528082747.3631-7-tomi.valkeinen@ti.com
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/bridge/tc358767.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index 119cd8d14d4b..39a9de880e5a 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -542,7 +542,6 @@ static int tc_aux_link_setup(struct tc_data *tc) unsigned long rate; u32 value; int ret; - u32 dp_phy_ctrl; rate = clk_get_rate(tc->refclk); switch (rate) { @@ -567,10 +566,7 @@ static int tc_aux_link_setup(struct tc_data *tc) value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2; tc_write(SYS_PLLPARAM, value); - dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN; - if (tc->link.base.num_lanes == 2) - dp_phy_ctrl |= PHY_2LANE; - tc_write(DP_PHY_CTRL, dp_phy_ctrl); + tc_write(DP_PHY_CTRL, BGREN | PWR_SW_EN | PHY_A0_EN); /* * Initially PLLs are in bypass. Force PLL parameter update, @@ -587,8 +583,9 @@ static int tc_aux_link_setup(struct tc_data *tc) if (ret == -ETIMEDOUT) { dev_err(tc->dev, "Timeout waiting for PHY to become ready"); return ret; - } else if (ret) + } else if (ret) { goto err; + } /* Setup AUX link */ tc_write(DP0_AUXCFG1, AUX_RX_FILTER_EN | |