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| author | Maxime Ripard <maxime@cerno.tech> | 2020-09-03 10:01:03 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime@cerno.tech> | 2020-09-07 18:04:17 +0200 |
| commit | 9e30cfd0764e1018897b8f4830d1cffd59a3fe40 (patch) | |
| tree | 5d94f4705750f943c84151716124780137116422 /drivers | |
| parent | 0d2b96af53c973942c8c5a2c6629915774bae187 (diff) | |
| download | lwn-9e30cfd0764e1018897b8f4830d1cffd59a3fe40.tar.gz lwn-9e30cfd0764e1018897b8f4830d1cffd59a3fe40.zip | |
drm/vc4: crtc: Clear the PixelValve FIFO during configuration
Even though it's not really clear why we need to flush the PV FIFO during
the configuration even though we started by flushing it, experience shows
that without it we get a stale pixel stuck in the FIFO between the HVS and
the PV.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ccd6269ba37b2f849ba6e62471c99bd93a4548a0.1599120059.git-series.maxime@cerno.tech
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/vc4/vc4_crtc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 73d918706f7e..00b2c2b011d1 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -358,7 +358,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc) if (is_dsi) CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); - CRTC_WRITE(PV_CONTROL, + CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) | VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) | |