diff options
| author | Michael Ira Krufky <mkrufky@linuxtv.org> | 2014-12-21 18:54:50 -0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@osg.samsung.com> | 2015-01-29 18:32:01 -0200 |
| commit | 27f7ef7ca952cf39214520248b2d792add756117 (patch) | |
| tree | 9b83c2dd573ff63b61d84d1b06f58ba554285fb1 /drivers | |
| parent | bdba90df2e30e98d192121117aaca545875d9f39 (diff) | |
| download | lwn-27f7ef7ca952cf39214520248b2d792add756117.tar.gz lwn-27f7ef7ca952cf39214520248b2d792add756117.zip | |
[media] lgdt3305: add support for fixed tp clock mode
Add support for controlling TP clock mode for VSB and QAM annex-B/C mode.
Gated clock mode is the default value, and does not support QAM annex-C.
The patch enables setting this control to fixed clock mode.
Signed-off-by: Michael Ira Krufky <mkrufky@linuxtv.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/media/dvb-frontends/lgdt3305.c | 3 | ||||
| -rw-r--r-- | drivers/media/dvb-frontends/lgdt3305.h | 6 |
2 files changed, 9 insertions, 0 deletions
diff --git a/drivers/media/dvb-frontends/lgdt3305.c b/drivers/media/dvb-frontends/lgdt3305.c index 13dddaf3ba10..d08570af1c10 100644 --- a/drivers/media/dvb-frontends/lgdt3305.c +++ b/drivers/media/dvb-frontends/lgdt3305.c @@ -241,6 +241,7 @@ static int lgdt3305_mpeg_mode_polarity(struct lgdt3305_state *state) u8 val; int ret; enum lgdt3305_tp_clock_edge edge = state->cfg->tpclk_edge; + enum lgdt3305_tp_clock_mode mode = state->cfg->tpclk_mode; enum lgdt3305_tp_valid_polarity valid = state->cfg->tpvalid_polarity; lg_dbg("edge = %d, valid = %d\n", edge, valid); @@ -253,6 +254,8 @@ static int lgdt3305_mpeg_mode_polarity(struct lgdt3305_state *state) if (edge) val |= 0x08; + if (mode) + val |= 0x40; if (valid) val |= 0x01; diff --git a/drivers/media/dvb-frontends/lgdt3305.h b/drivers/media/dvb-frontends/lgdt3305.h index d9ab556c1b27..9c03e530e01b 100644 --- a/drivers/media/dvb-frontends/lgdt3305.h +++ b/drivers/media/dvb-frontends/lgdt3305.h @@ -37,6 +37,11 @@ enum lgdt3305_tp_clock_edge { LGDT3305_TPCLK_FALLING_EDGE = 1, }; +enum lgdt3305_tp_clock_mode { + LGDT3305_TPCLK_GATED = 0, + LGDT3305_TPCLK_FIXED = 1, +}; + enum lgdt3305_tp_valid_polarity { LGDT3305_TP_VALID_LOW = 0, LGDT3305_TP_VALID_HIGH = 1, @@ -70,6 +75,7 @@ struct lgdt3305_config { enum lgdt3305_mpeg_mode mpeg_mode; enum lgdt3305_tp_clock_edge tpclk_edge; + enum lgdt3305_tp_clock_mode tpclk_mode; enum lgdt3305_tp_valid_polarity tpvalid_polarity; enum lgdt_demod_chip_type demod_chip; }; |