diff options
| author | Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> | 2018-03-14 11:26:52 -0700 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2018-03-15 08:46:06 +0000 |
| commit | 210060edc216ebd6330ee4fded5a01547d938642 (patch) | |
| tree | 7e957f316f413091f5e58003d9b9ff94329a8cd5 /drivers | |
| parent | 74419daaae6c1dafe9cc5d4d0c92c17982f4eebd (diff) | |
| download | lwn-210060edc216ebd6330ee4fded5a01547d938642.tar.gz lwn-210060edc216ebd6330ee4fded5a01547d938642.zip | |
drm/i915: use engine->irq_keep_mask when resetting irqs
The "reset" value and the "keep" value are the same.
While we are here, add a TODO for gen11 interrupt reset
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180314182653.26981-3-daniele.ceraolospurio@intel.com
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_lrc.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 3a69b367e565..5e8f6896d059 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1666,6 +1666,10 @@ static void reset_irq(struct intel_engine_cs *engine) struct drm_i915_private *dev_priv = engine->i915; int i; + /* TODO: correctly reset irqs for gen11 */ + if (WARN_ON_ONCE(INTEL_GEN(engine->i915) >= 11)) + return; + GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir)); /* @@ -1677,11 +1681,11 @@ static void reset_irq(struct intel_engine_cs *engine) */ for (i = 0; i < 2; i++) { I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]), - GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift); + engine->irq_keep_mask); POSTING_READ(GEN8_GT_IIR(gtiir[engine->id])); } GEM_BUG_ON(I915_READ(GEN8_GT_IIR(gtiir[engine->id])) & - (GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift)); + engine->irq_keep_mask); clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); } |