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| author | Jeremy Fitzhardinge <jeremy@goop.org> | 2009-09-03 12:27:15 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2009-09-24 08:44:01 -0700 |
| commit | 1cde5a2e3f782234336582558dd8591f811bfb55 (patch) | |
| tree | fb378fefe7fe6fb9b64ad5f87781c818812f5d5c /drivers | |
| parent | 2d75a4795020ccdfaae36c4ecb004d8c0fc35708 (diff) | |
| download | lwn-1cde5a2e3f782234336582558dd8591f811bfb55.tar.gz lwn-1cde5a2e3f782234336582558dd8591f811bfb55.zip | |
x86/i386: Make sure stack-protector segment base is cache aligned
commit 1ea0d14e480c245683927eecc03a70faf06e80c8 upstream.
The Intel Optimization Reference Guide says:
In Intel Atom microarchitecture, the address generation unit
assumes that the segment base will be 0 by default. Non-zero
segment base will cause load and store operations to experience
a delay.
- If the segment base isn't aligned to a cache line
boundary, the max throughput of memory operations is
reduced to one [e]very 9 cycles.
[...]
Assembly/Compiler Coding Rule 15. (H impact, ML generality)
For Intel Atom processors, use segments with base set to 0
whenever possible; avoid non-zero segment base address that is
not aligned to cache line boundary at all cost.
We can't avoid having a non-zero base for the stack-protector
segment, but we can make it cache-aligned.
Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
LKML-Reference: <4AA01893.6000507@goop.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
0 files changed, 0 insertions, 0 deletions