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| author | Archit Taneja <archit@ti.com> | 2011-09-13 18:28:41 +0530 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2011-09-30 16:17:25 +0300 |
| commit | c3dc6a7afb47735b82a4c0061e814454a649dbfc (patch) | |
| tree | d04f7a341aed9d9aae42d33479526f9d26c7e74b /drivers/video/omap2/dss/hdmi.c | |
| parent | dac57a05fcf4808bbc91a96a034cae84716f0077 (diff) | |
| download | lwn-c3dc6a7afb47735b82a4c0061e814454a649dbfc.tar.gz lwn-c3dc6a7afb47735b82a4c0061e814454a649dbfc.zip | |
OMAPDSS: DISPC: Get correct pixel clock for TV manager
dispc_mgr_pclk_rate() is used to calculate minimum required functional clock for
scaling in calc_fclk() and calc_fclk_five_taps(). This function returns the
correct pixel clock for LCD and LCD2 managers, but not for TV manager. Extend
this function so that it gets the correct pixel clock for TV manager.
This also prevents the crash we get when we try to scale overlays connected to
TV manager. The current code leads to a BUG() being executed if we call
dispc_mgr_pclk_rate() for the TV manager.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/hdmi.c')
| -rw-r--r-- | drivers/video/omap2/dss/hdmi.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c index 781867002662..2f554ae6858e 100644 --- a/drivers/video/omap2/dss/hdmi.c +++ b/drivers/video/omap2/dss/hdmi.c @@ -266,6 +266,12 @@ static void update_hdmi_timings(struct hdmi_config *cfg, cfg->timings.hsync_pol = cea_vesa_timings[code].hsync_pol; } +unsigned long hdmi_get_pixel_clock(void) +{ + /* HDMI Pixel Clock in Mhz */ + return hdmi.ip_data.cfg.timings.timings.pixel_clock * 10000; +} + static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, struct hdmi_pll_info *pi) { |