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| author | Sandeep Maheswaram <quic_c_sanm@quicinc.com> | 2021-10-25 09:49:35 +0530 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2021-10-26 16:36:23 +0530 |
| commit | b475bf0ec40a2b13fb32ef62f5706576d5858460 (patch) | |
| tree | 2dfd7d72bf2631e9282baa28cb75ac55dd8b7efd /drivers/phy/qualcomm | |
| parent | 21b89120be87b3fd2454e354bf466e5c4fea9624 (diff) | |
| download | lwn-b475bf0ec40a2b13fb32ef62f5706576d5858460.tar.gz lwn-b475bf0ec40a2b13fb32ef62f5706576d5858460.zip | |
phy: qcom-snps: Correct the FSEL_MASK
The FSEL_MASK which selects the refclock is defined incorrectly.
It should be [4:6] not [5:7]. Due to this incorrect definition, the BIT(7)
in USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 is reset which keeps PHY analog
blocks ON during suspend.
Fix this issue by correctly defining the FSEL_MASK.
Fixes: 51e8114f80d0 ("phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCs")
Signed-off-by: Sandeep Maheswaram <quic_c_sanm@quicinc.com>
Link: https://lore.kernel.org/r/1635135575-5668-1-git-send-email-quic_c_sanm@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy/qualcomm')
| -rw-r--r-- | drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c index ae4bac024c7b..7e61202aa234 100644 --- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c +++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c @@ -33,7 +33,7 @@ #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) #define RETENABLEN BIT(3) -#define FSEL_MASK GENMASK(7, 5) +#define FSEL_MASK GENMASK(6, 4) #define FSEL_DEFAULT (0x3 << 4) #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58) |