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| author | Sasha Neftin <sasha.neftin@intel.com> | 2019-08-08 09:12:23 +0300 |
|---|---|---|
| committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2019-09-09 11:37:14 -0700 |
| commit | d3ae3cfbf5484f18b86b708b71c416c63d3bb922 (patch) | |
| tree | de03c5c78210e8a6d04f75fa9c3d7e9f2869ab80 /drivers/net/ethernet/intel/igc/igc.h | |
| parent | e7ba676c6188d394a0133fc4b9bcd7ee50d54b7f (diff) | |
| download | lwn-d3ae3cfbf5484f18b86b708b71c416c63d3bb922.tar.gz lwn-d3ae3cfbf5484f18b86b708b71c416c63d3bb922.zip | |
igc: Add tx_csum offload functionality
Add IP generic TX checksum offload functionality.
Signed-off-by: Sasha Neftin <sasha.neftin@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/igc/igc.h')
| -rw-r--r-- | drivers/net/ethernet/intel/igc/igc.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/intel/igc/igc.h index 0f5534ce27b0..7e16345d836e 100644 --- a/drivers/net/ethernet/intel/igc/igc.h +++ b/drivers/net/ethernet/intel/igc/igc.h @@ -135,6 +135,9 @@ extern char igc_driver_version[]; /* How many Rx Buffers do we bundle into one write to the hardware ? */ #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ +/* VLAN info */ +#define IGC_TX_FLAGS_VLAN_MASK 0xffff0000 + /* igc_test_staterr - tests bits within Rx descriptor status and error fields */ static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, const u32 stat_err_bits) @@ -254,6 +257,7 @@ struct igc_ring { u16 count; /* number of desc. in the ring */ u8 queue_index; /* logical index of the ring*/ u8 reg_idx; /* physical index of the ring */ + bool launchtime_enable; /* true if LaunchTime is enabled */ /* everything past this point are written often */ u16 next_to_clean; |