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| author | Dinh Nguyen <dinguyen@kernel.org> | 2022-11-14 17:02:16 -0600 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2022-12-07 13:22:37 +0100 |
| commit | d0ce6aca9ddf1177d9f2757c9fed502682934343 (patch) | |
| tree | 7eca4114c79ed7e256311a817fb4c546b8c0d955 /drivers/mmc/core/pwrseq.c | |
| parent | ef87bd81cb881377c1eaf512167b0522c825b012 (diff) | |
| download | lwn-d0ce6aca9ddf1177d9f2757c9fed502682934343.tar.gz lwn-d0ce6aca9ddf1177d9f2757c9fed502682934343.zip | |
clk: socfpga: remove the setting of clk-phase for sdmmc_clk
Now that the SDMMC driver supports setting the clk-phase, we can remove
the need to do it in the clock driver.
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20221114230217.202634-5-dinguyen@kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc/core/pwrseq.c')
0 files changed, 0 insertions, 0 deletions