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| author | Dmitry Osipenko <digetx@gmail.com> | 2018-12-12 23:38:52 +0300 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2019-01-16 13:54:11 +0100 |
| commit | 96efa118c03648fdc76acad9ca8fe018a6be7145 (patch) | |
| tree | f4efbd5dc8ab97aa842ef37a81290016c100ece9 /drivers/memory/tegra/mc.h | |
| parent | be4dbdec2bab8635c7a41573668624ee13d83022 (diff) | |
| download | lwn-96efa118c03648fdc76acad9ca8fe018a6be7145.tar.gz lwn-96efa118c03648fdc76acad9ca8fe018a6be7145.zip | |
memory: tegra: Adapt to Tegra20 device-tree binding changes
The tegra20-mc device-tree binding has been changed, GART has been
squashed into Memory Controller and now the clock property is mandatory
for Tegra20, the DT compatible has been changed as well. Adapt driver to
the DT changes.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers/memory/tegra/mc.h')
| -rw-r--r-- | drivers/memory/tegra/mc.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 01065f12ebeb..9856f085e487 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -26,18 +26,12 @@ static inline u32 mc_readl(struct tegra_mc *mc, unsigned long offset) { - if (mc->regs2 && offset >= 0x24) - return readl(mc->regs2 + offset - 0x3c); - return readl(mc->regs + offset); } static inline void mc_writel(struct tegra_mc *mc, u32 value, unsigned long offset) { - if (mc->regs2 && offset >= 0x24) - return writel(value, mc->regs2 + offset - 0x3c); - writel(value, mc->regs + offset); } |