diff options
| author | Hari Prasath <Hari.PrasathGE@microchip.com> | 2024-09-03 12:12:52 +0530 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2024-10-02 15:36:47 +0200 |
| commit | e408b0131644b0b3e7ab880aad905ca0c8ca8ad0 (patch) | |
| tree | d996314d1435dae91cd9f16d120ad508294fc488 /drivers/irqchip | |
| parent | 5a5d6753035451027a6ae92f478eb0b07f801348 (diff) | |
| download | lwn-e408b0131644b0b3e7ab880aad905ca0c8ca8ad0.tar.gz lwn-e408b0131644b0b3e7ab880aad905ca0c8ca8ad0.zip | |
irqchip/atmel-aic5: Add support for sam9x7 aic
Add support for the Advanced interrupt controller(AIC) chip in the sam9x7.
Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/all/20240903064252.49530-1-varshini.rajendran@microchip.com
Diffstat (limited to 'drivers/irqchip')
| -rw-r--r-- | drivers/irqchip/irq-atmel-aic5.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c index c0f55dc7b050..e98c2875af9e 100644 --- a/drivers/irqchip/irq-atmel-aic5.c +++ b/drivers/irqchip/irq-atmel-aic5.c @@ -319,6 +319,7 @@ static const struct of_device_id aic5_irq_fixups[] __initconst = { { .compatible = "atmel,sama5d3", .data = sama5d3_aic_irq_fixup }, { .compatible = "atmel,sama5d4", .data = sama5d3_aic_irq_fixup }, { .compatible = "microchip,sam9x60", .data = sam9x60_aic_irq_fixup }, + { .compatible = "microchip,sam9x7", .data = sam9x60_aic_irq_fixup }, { /* sentinel */ }, }; @@ -405,3 +406,11 @@ static int __init sam9x60_aic5_of_init(struct device_node *node, return aic5_of_init(node, parent, NR_SAM9X60_IRQS); } IRQCHIP_DECLARE(sam9x60_aic5, "microchip,sam9x60-aic", sam9x60_aic5_of_init); + +#define NR_SAM9X7_IRQS 70 + +static int __init sam9x7_aic5_of_init(struct device_node *node, struct device_node *parent) +{ + return aic5_of_init(node, parent, NR_SAM9X7_IRQS); +} +IRQCHIP_DECLARE(sam9x7_aic5, "microchip,sam9x7-aic", sam9x7_aic5_of_init); |