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author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-02-26 15:32:00 +0100 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-02-26 15:32:00 +0100 |
commit | 36e9f7203e05090031a5356be043a9be342e383c (patch) | |
tree | 27877737c3bb3c00ee9caeece7d671f65cf91252 /drivers/hwmon/coretemp.c | |
parent | 721dfe4133a9a41e4b4a74e5b41089b7dac8f539 (diff) | |
parent | 4a3928c6f8a53fa1aed28ccba227742486e8ddcb (diff) | |
download | lwn-36e9f7203e05090031a5356be043a9be342e383c.tar.gz lwn-36e9f7203e05090031a5356be043a9be342e383c.zip |
Merge 4.16-rc3 into staging-next
We want the IIO/Staging fixes in here, and to resolve a merge problem
with the move of the fsl-mc code.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/hwmon/coretemp.c')
-rw-r--r-- | drivers/hwmon/coretemp.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c index 4bdbf77f7197..72c338eb5fae 100644 --- a/drivers/hwmon/coretemp.c +++ b/drivers/hwmon/coretemp.c @@ -269,13 +269,13 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) for (i = 0; i < ARRAY_SIZE(tjmax_model_table); i++) { const struct tjmax_model *tm = &tjmax_model_table[i]; if (c->x86_model == tm->model && - (tm->mask == ANY || c->x86_mask == tm->mask)) + (tm->mask == ANY || c->x86_stepping == tm->mask)) return tm->tjmax; } /* Early chips have no MSR for TjMax */ - if (c->x86_model == 0xf && c->x86_mask < 4) + if (c->x86_model == 0xf && c->x86_stepping < 4) usemsr_ee = 0; if (c->x86_model > 0xe && usemsr_ee) { @@ -426,7 +426,7 @@ static int chk_ucode_version(unsigned int cpu) * Readings might stop update when processor visited too deep sleep, * fixed for stepping D0 (6EC). */ - if (c->x86_model == 0xe && c->x86_mask < 0xc && c->microcode < 0x39) { + if (c->x86_model == 0xe && c->x86_stepping < 0xc && c->microcode < 0x39) { pr_err("Errata AE18 not fixed, update BIOS or microcode of the CPU!\n"); return -ENODEV; } |