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author | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2015-09-07 17:34:26 +0300 |
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committer | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2016-02-23 09:34:29 +0200 |
commit | 2427b3037710d4aa71c9c1cdfcd542805e0c53f3 (patch) | |
tree | 810b6fb9005f3471e65acbace0453f10a4faf1da /drivers/gpu/drm/rcar-du/rcar_du_regs.h | |
parent | a5e18b2b7d5d9486c27142f0a76565954160ab3b (diff) | |
download | lwn-2427b3037710d4aa71c9c1cdfcd542805e0c53f3.tar.gz lwn-2427b3037710d4aa71c9c1cdfcd542805e0c53f3.zip |
drm: rcar-du: Add R8A7795 device support
Document the R8A7795-specific DT bindings and support them in the
driver. The HDMI and LVDS outputs are currently not supported.
Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Diffstat (limited to 'drivers/gpu/drm/rcar-du/rcar_du_regs.h')
-rw-r--r-- | drivers/gpu/drm/rcar-du/rcar_du_regs.h | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_regs.h b/drivers/gpu/drm/rcar-du/rcar_du_regs.h index 2ccb1a241fc4..d2f66068e52c 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_regs.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_regs.h @@ -1,7 +1,7 @@ /* * rcar_du_regs.h -- R-Car Display Unit Registers Definitions * - * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013-2015 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * @@ -261,6 +261,21 @@ #define DIDSR_PDCS_CLK(n, clk) (clk << ((n) * 2)) #define DIDSR_PDCS_MASK(n) (3 << ((n) * 2)) +#define DEFR10 0x20038 +#define DEFR10_CODE (0x7795 << 16) +#define DEFR10_VSPF1_RGB (0 << 14) +#define DEFR10_VSPF1_YC (1 << 14) +#define DEFR10_DOCF1_RGB (0 << 12) +#define DEFR10_DOCF1_YC (1 << 12) +#define DEFR10_YCDF0_YCBCR444 (0 << 11) +#define DEFR10_YCDF0_YCBCR422 (1 << 11) +#define DEFR10_VSPF0_RGB (0 << 10) +#define DEFR10_VSPF0_YC (1 << 10) +#define DEFR10_DOCF0_RGB (0 << 8) +#define DEFR10_DOCF0_YC (1 << 8) +#define DEFR10_TSEL_H3_TCON1 (0 << 1) /* DEFR102 register only (DU2/DU3) */ +#define DEFR10_DEFE10 (1 << 0) + /* ----------------------------------------------------------------------------- * Display Timing Generation Registers */ |