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authorAlex Deucher <alexander.deucher@amd.com>2014-01-27 11:26:33 -0500
committerAlex Deucher <alexander.deucher@amd.com>2014-01-29 15:23:05 -0500
commit50efa51afddb50a6ab47ee15614fcf180130888c (patch)
tree5f80ce2157217fe83c3569a484e03c2e15f5e4d7 /drivers/gpu/drm/radeon/ni.c
parentb9ace36f13c6fc46391c9d40edc648eef3a59ab0 (diff)
downloadlwn-50efa51afddb50a6ab47ee15614fcf180130888c.tar.gz
lwn-50efa51afddb50a6ab47ee15614fcf180130888c.zip
drm/radeon: clean up active vram sizing
If we are not able to properly initialize one of the gpu engines for buffer paging, we limit vram to the size of the cpu visible aperture. We generally either use the gfx or dma engine to do this. Clean up the size limiting code to only adjust the size based on what ring is selected for buffer paging rather than making assumptions about which engine is selected for paging. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/ni.c')
-rw-r--r--drivers/gpu/drm/radeon/ni.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 647b1d0fa62c..ea932ac66fc6 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1390,7 +1390,8 @@ static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
if (enable)
WREG32(CP_ME_CNTL, 0);
else {
- radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
+ if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
+ radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
WREG32(SCRATCH_UMSK, 0);
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
@@ -1663,6 +1664,9 @@ static int cayman_cp_resume(struct radeon_device *rdev)
return r;
}
+ if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
+ radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
+
return 0;
}