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authorAlex Deucher <alexander.deucher@amd.com>2014-11-18 14:36:59 -0500
committerAlex Deucher <alexander.deucher@amd.com>2014-11-20 13:00:12 -0500
commite745c3c9aa5e30ae94a1be04a1d2f326fb213a56 (patch)
tree7f42088076daeea7da0763d758f3c12bd17e0ee4 /drivers/gpu/drm/radeon/ci_dpm.c
parentf281d0a37c423cb4cc8ef91ba7136848744c955f (diff)
downloadlwn-e745c3c9aa5e30ae94a1be04a1d2f326fb213a56.tar.gz
lwn-e745c3c9aa5e30ae94a1be04a1d2f326fb213a56.zip
drm/radeon/ci: use different smc command for pcie dpm
Use unforce levels rather than enable mask instruction. This is the preferred method. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/ci_dpm.c')
-rw-r--r--drivers/gpu/drm/radeon/ci_dpm.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index e7816281f0d7..73f8c4b5bc9c 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -3773,7 +3773,7 @@ static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
return -EINVAL;
}
}
-
+#if 0
if (!pi->pcie_dpm_key_disabled) {
if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
result = ci_send_msg_to_smc_with_parameter(rdev,
@@ -3783,7 +3783,7 @@ static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
return -EINVAL;
}
}
-
+#endif
return 0;
}
@@ -4247,6 +4247,14 @@ int ci_dpm_force_performance_level(struct radeon_device *rdev,
}
}
} else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
+ if (!pi->pcie_dpm_key_disabled) {
+ PPSMC_Result smc_result;
+
+ smc_result = ci_send_msg_to_smc(rdev,
+ PPSMC_MSG_PCIeDPM_UnForceLevel);
+ if (smc_result != PPSMC_Result_OK)
+ return -EINVAL;
+ }
ret = ci_upload_dpm_level_enable_mask(rdev);
if (ret)
return ret;