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| author | Neil Armstrong <narmstrong@baylibre.com> | 2019-10-21 11:15:01 +0200 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2019-12-10 10:08:09 +0100 |
| commit | 26a7abd4883b71b33371e6ded32422d4e5f9c1c5 (patch) | |
| tree | 023ee3907c3683944ad67392ee024382d43aab49 /drivers/gpu/drm/meson/meson_viu.h | |
| parent | b0077e521c8af7761404ae772a328e5f0bf15094 (diff) | |
| download | lwn-26a7abd4883b71b33371e6ded32422d4e5f9c1c5.tar.gz lwn-26a7abd4883b71b33371e6ded32422d4e5f9c1c5.zip | |
drm/meson: add AFBC decoder registers for GXM and G12A
Add the registers used to program the ARM Framebuffer Compression decoders
used in the Amlogic GXM and G12A SoCs families.
This also adds the routing and pipeline configuration bits and registers
needed to enable AFBC support.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-2-narmstrong@baylibre.com
Diffstat (limited to 'drivers/gpu/drm/meson/meson_viu.h')
| -rw-r--r-- | drivers/gpu/drm/meson/meson_viu.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/gpu/drm/meson/meson_viu.h b/drivers/gpu/drm/meson/meson_viu.h index a112e8d18850..e297772d967f 100644 --- a/drivers/gpu/drm/meson/meson_viu.h +++ b/drivers/gpu/drm/meson/meson_viu.h @@ -10,6 +10,8 @@ #define __MESON_VIU_H /* OSDx_BLKx_CFG */ +#define OSD_MALI_SRC_EN BIT(30) + #define OSD_CANVAS_SEL 16 #define OSD_ENDIANNESS_LE BIT(15) @@ -33,19 +35,32 @@ #define OSD_COLOR_MATRIX_16_RGB655 (0x00 << 2) #define OSD_COLOR_MATRIX_16_RGB565 (0x04 << 2) +#define OSD_MALI_COLOR_MODE_R8 (0 << 8) +#define OSD_MALI_COLOR_MODE_YUV422 (1 << 8) +#define OSD_MALI_COLOR_MODE_RGB565 (2 << 8) +#define OSD_MALI_COLOR_MODE_RGBA5551 (3 << 8) +#define OSD_MALI_COLOR_MODE_RGBA4444 (4 << 8) +#define OSD_MALI_COLOR_MODE_RGBA8888 (5 << 8) +#define OSD_MALI_COLOR_MODE_RGB888 (7 << 8) +#define OSD_MALI_COLOR_MODE_YUV422_10B (8 << 8) +#define OSD_MALI_COLOR_MODE_RGBA1010102 (9 << 8) + #define OSD_INTERLACE_ENABLED BIT(1) #define OSD_INTERLACE_ODD BIT(0) #define OSD_INTERLACE_EVEN (0) /* OSDx_CTRL_STAT */ #define OSD_ENABLE BIT(21) +#define OSD_MEM_LINEAR_ADDR BIT(2) #define OSD_BLK0_ENABLE BIT(0) #define OSD_GLOBAL_ALPHA_SHIFT 12 /* OSDx_CTRL_STAT2 */ +#define OSD_DPATH_MALI_AFBCD BIT(15) #define OSD_REPLACE_EN BIT(14) #define OSD_REPLACE_SHIFT 6 +#define OSD_PENDING_STAT_CLEAN BIT(1) void meson_viu_osd1_reset(struct meson_drm *priv); void meson_viu_init(struct meson_drm *priv); |