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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2012-10-05 12:05:54 -0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-10-10 15:48:16 +0200 |
| commit | fc914639b12054c930fe75a2ff4221311699e9c2 (patch) | |
| tree | 6939d0f1dc182f6539d788e291bd0e92f81c3522 /drivers/gpu/drm/i915/intel_drv.h | |
| parent | 8d9ddbcbd0e3fc9368a5972346dc726493d31c9c (diff) | |
| download | lwn-fc914639b12054c930fe75a2ff4221311699e9c2.tar.gz lwn-fc914639b12054c930fe75a2ff4221311699e9c2.zip | |
drm/i915: enable and disable PIPE_CLK_SEL at the right time
Previously we were enabling it at mode_set but never disabling. Let's
follow the mode set sequence.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_drv.h')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_drv.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 0253bb4b70fd..5de365d70de9 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -584,5 +584,7 @@ extern void intel_ddi_pll_init(struct drm_device *dev); extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc); extern void intel_ddi_disable_pipe_func(struct drm_i915_private *dev_priv, enum pipe pipe); +extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); +extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); #endif /* __INTEL_DRV_H__ */ |