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| author | Damien Lespiau <damien.lespiau@intel.com> | 2015-06-25 16:19:24 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-06-26 19:39:31 +0200 |
| commit | 267db663458a8077a087674fb85ea95f540d8671 (patch) | |
| tree | b50993dd5022ffecf2c4e2197ad35dbd758d2266 /drivers/gpu/drm/i915/intel_ddi.c | |
| parent | dc2538139277089e218b1b1d0d01454ecf39e944 (diff) | |
| download | lwn-267db663458a8077a087674fb85ea95f540d8671.tar.gz lwn-267db663458a8077a087674fb85ea95f540d8671.zip | |
drm/i915/skl: Prefer even dividers for SKL DPLLs
Currently, if an odd divider improves the deviation (minimizes it), we
take that divider. The recommendation is to prefer even dividers.
v2: Move the check at the right place after having inverted the two for
loops in the previous patch.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ddi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ddi.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 6e964ef7dfda..f6b3ccc4ab66 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1317,6 +1317,13 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */, p); } } + + /* + * If a solution is found with an even divider, prefer + * this one. + */ + if (d == 0 && ctx.p) + break; } if (!ctx.p) { |