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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-06-05 13:34:28 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-07-01 11:27:53 +0200 |
| commit | 8bcc2795a68ad9c2010fd5a2548432fad930fcc1 (patch) | |
| tree | 7e70203c9cd1521ee2c850ee851beee5469249c6 /drivers/gpu/drm/i915/i915_drv.h | |
| parent | 952735ee416f686fac55957b221461dfbd80ce1c (diff) | |
| download | lwn-8bcc2795a68ad9c2010fd5a2548432fad930fcc1.tar.gz lwn-8bcc2795a68ad9c2010fd5a2548432fad930fcc1.zip | |
drm/i915: hw state readout for i9xx dplls
In addition to existing stuff we also need to track DPLL_MD on gen4
and vlv. This is prep work so that we can move the dpll enable
sequence out from the ->mode_set callback into the crtc enabling
functions.
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index dfb10fee83b6..e9c8b588e14d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -144,6 +144,7 @@ enum intel_dpll_id { struct intel_dpll_hw_state { uint32_t dpll; + uint32_t dpll_md; uint32_t fp0; uint32_t fp1; }; |