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| author | Khaled Almahallawy <khaled.almahallawy@intel.com> | 2023-10-04 17:13:10 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-10-17 22:08:49 -0400 |
| commit | 5e4c16fe08c8b894b258f4110349dc9b642669f9 (patch) | |
| tree | 2d4dc808a0e91d2491b6c5e17a8018ac1d2051d2 /drivers/gpu/drm/i915/gem/i915_gem_mman.c | |
| parent | 58720809f52779dc0f08e53e54b014209d13eebb (diff) | |
| download | lwn-5e4c16fe08c8b894b258f4110349dc9b642669f9.tar.gz lwn-5e4c16fe08c8b894b258f4110349dc9b642669f9.zip | |
drm/i915/cx0: Only clear/set the Pipe Reset bit of the PHY Lanes Owned
Currently, with MFD/pin assignment D, the driver clears the pipe reset bit
of lane 1 which is not owned by display. This causes the display
to block S0iX.
By not clearing this bit for lane 1 and keeping whatever default, S0ix
started to work. This is already what the driver does at the end
of the phy lane reset sequence (Step#8)
Bspec: 65451
Fixes: 619a06dba6fa ("drm/i915/mtl: Reset only one lane in case of MFD")
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231005001310.154396-1-khaled.almahallawy@intel.com
(cherry picked from commit 4a07f063d20c46524f00976f4537de72d9f31c4e)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gem/i915_gem_mman.c')
0 files changed, 0 insertions, 0 deletions