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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-06-12 23:47:12 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-06-24 17:14:55 +0300 |
| commit | f8fa26f4e09230137a304a5275d2633a6de11c7d (patch) | |
| tree | 317c6cf6981eb57d161fce0231b4b6e8d51a9f6b /drivers/gpu/drm/i915/display/intel_fb.c | |
| parent | 7652126ce7070ddcd1b3f8791efcf7537a9ec01e (diff) | |
| download | lwn-f8fa26f4e09230137a304a5275d2633a6de11c7d.tar.gz lwn-f8fa26f4e09230137a304a5275d2633a6de11c7d.zip | |
drm/i915: Nuke the TGL+ chroma plane tile row alignment stuff
I don't think the display hardware really has such chroma
plane tile row alignment requirements as outlined in
commit d156135e6a54 ("drm/i915/tgl: Make sure a semiplanar
UV plane is tile row size aligned")
Bspec had the same exact thing to say about earlier hardware
as well, but we never cared and things work just fine.
The one thing mentioned in that commit that is definitely
true however is the fence alignment issue. But we don't
deal with that on earlier hardware either. We do have code
to deal with that issue for the first color plane, but not
the chroma planes. So I think if we did want to check this
more extensively we should do it in the same places where
we already check the first color plane (namely
convert_plane_offset_to_xy() and intel_fb_bo_framebuffer_init()).
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240612204712.31404-10-ville.syrjala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_fb.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_fb.c | 12 |
1 files changed, 1 insertions, 11 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index a11c1cf6f548..f23547a88b1f 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -585,12 +585,6 @@ static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int color_pl return intel_fb_rc_ccs_cc_plane(fb) == color_plane; } -bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane) -{ - return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && - color_plane == 1; -} - bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane) { return fb->modifier == DRM_FORMAT_MOD_LINEAR || @@ -1020,11 +1014,7 @@ static int intel_fb_offset_to_xy(int *x, int *y, struct drm_i915_private *i915 = to_i915(fb->dev); unsigned int height, alignment, unused; - if (DISPLAY_VER(i915) >= 12 && - !intel_fb_needs_pot_stride_remap(to_intel_framebuffer(fb)) && - is_semiplanar_uv_plane(fb, color_plane)) - alignment = intel_tile_row_size(fb, color_plane); - else if (fb->modifier != DRM_FORMAT_MOD_LINEAR) + if (fb->modifier != DRM_FORMAT_MOD_LINEAR) alignment = intel_tile_size(i915); else alignment = 0; |