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| author | Tony Cheng <tony.cheng@amd.com> | 2017-11-22 11:51:30 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-12-14 10:55:09 -0500 |
| commit | 75c2dec31a100daee4d3d9a1c2042918c9561f04 (patch) | |
| tree | 01e8779a0fecea5e914a5f1ab7c9e498274c92f8 /drivers/gpu/drm/amd | |
| parent | a018298ff850effd3a8494c839449150aef0934a (diff) | |
| download | lwn-75c2dec31a100daee4d3d9a1c2042918c9561f04.tar.gz lwn-75c2dec31a100daee4d3d9a1c2042918c9561f04.zip | |
drm/amd/display: really fix time out in init sequence
REG_UPDATE_2 return the reg value it write out through MMIO
we need to do a REG_READ to confirm the value is written out
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c index 1984ac2eb740..2d843b2d5f86 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c @@ -42,13 +42,14 @@ void hubp1_set_blank(struct hubp *hubp, bool blank) { struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); uint32_t blank_en = blank ? 1 : 0; - uint32_t reg_val = 0; - reg_val = REG_UPDATE_2(DCHUBP_CNTL, + REG_UPDATE_2(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en, HUBP_TTU_DISABLE, blank_en); if (blank) { + uint32_t reg_val = REG_READ(DCHUBP_CNTL); + if (reg_val) { /* init sequence workaround: in case HUBP is * power gated, this wait would timeout. |