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| author | Andrew Jiang <Andrew.Jiang@amd.com> | 2017-11-21 15:59:42 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-12-14 10:54:31 -0500 |
| commit | 16a29dd3bb18ea23d9676e6a3b1c6464dba620c3 (patch) | |
| tree | 41a0c3a1b62dd73fb84f00b3c406395b6a18adc0 /drivers/gpu/drm/amd | |
| parent | ea783c31e270dbdd82d5b9d40de4e6336e92e5b2 (diff) | |
| download | lwn-16a29dd3bb18ea23d9676e6a3b1c6464dba620c3.tar.gz lwn-16a29dd3bb18ea23d9676e6a3b1c6464dba620c3.zip | |
drm/amd/display: Refine update flags usage in update_dchubp_dpp
- Only update DPP clock if it's a full update.
- Program viewport on position change. This caused SLS regressions.
Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index e9ecbcb66e80..7846534cd6d5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1726,7 +1726,7 @@ static void update_dchubp_dpp( union plane_size size = plane_state->plane_size; /* depends on DML calculation, DPP clock value may change dynamically */ - if (pipe_ctx->plane_state->update_flags.raw != 0) { + if (plane_state->update_flags.bits.full_update) { enable_dppclk( dc->hwseq, pipe_ctx->pipe_idx, @@ -1770,7 +1770,8 @@ static void update_dchubp_dpp( } if (plane_state->update_flags.bits.full_update || - plane_state->update_flags.bits.scaling_change) { + plane_state->update_flags.bits.scaling_change || + plane_state->update_flags.bits.position_change) { hubp->funcs->mem_program_viewport( hubp, &pipe_ctx->plane_res.scl_data.viewport, |