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| author | Boyuan Zhang <boyuan.zhang@amd.com> | 2018-07-18 16:24:18 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-08-27 11:10:10 -0500 |
| commit | 44287b7190f4504792e8bbfcd0ef899d566e4ec7 (patch) | |
| tree | 7dcb8935f90443157fdacecb46b32d834bd92a71 /drivers/gpu/drm/amd/include | |
| parent | 8709890892d839ba7169924a301c9cb0bd54ce6b (diff) | |
| download | lwn-44287b7190f4504792e8bbfcd0ef899d566e4ec7.tar.gz lwn-44287b7190f4504792e8bbfcd0ef899d566e4ec7.zip | |
drm/amdgpu: add system interrupt mask for jrbc
Add new mask for enabling system interrupt for jrbc.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h index d6ba26922275..124383dac284 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h @@ -982,6 +982,8 @@ #define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L #define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L +//UVD_SYS_INT_EN +#define UVD_SYS_INT_EN__UVD_JRBC_EN_MASK 0x00000010L //JPEG_CGC_CTRL #define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 #define JPEG_CGC_CTRL__JPEG2_MODE__SHIFT 0x1 |