diff options
| author | Charlene Liu <Charlene.Liu@amd.com> | 2024-07-16 13:47:43 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-07-27 17:32:15 -0400 |
| commit | 9724b8494d3e85cb01c377f201bfaf25fd7d38ff (patch) | |
| tree | 626f8411149aa073053a98e315098588f9182ed0 /drivers/gpu/drm/amd/display/dc/optc/dcn31 | |
| parent | 739d0f3e1f36738d4cd84166784a8f7a58d69612 (diff) | |
| download | lwn-9724b8494d3e85cb01c377f201bfaf25fd7d38ff.tar.gz lwn-9724b8494d3e85cb01c377f201bfaf25fd7d38ff.zip | |
drm/amd/display: restore immediate_disable_crtc for w/a
[why]
immediate_disable_crtc does not reset ODM. if switching to disable_crtc
which will disable ODM as well. i.e. need to restore ODM mem cfg at
reenable it at end of w/a.
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Xi (Alex) Liu <xi.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/optc/dcn31')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c index 6bbbf313b2bb..4b6446ed4ce4 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c @@ -149,7 +149,9 @@ static bool optc31_disable_crtc(struct timing_generator *optc) return true; } - +/* + * Immediate_Disable_Crtc - this is to temp disable Timing generator without reset ODM. + */ bool optc31_immediate_disable_crtc(struct timing_generator *optc) { struct optc *optc1 = DCN10TG_FROM_TG(optc); @@ -162,10 +164,12 @@ bool optc31_immediate_disable_crtc(struct timing_generator *optc) VTG0_ENABLE, 0); /* CRTC disabled, so disable clock. */ - REG_WAIT(OTG_CLOCK_CONTROL, + if (optc->ctx->dce_environment != DCE_ENV_DIAG) + REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000); + /* clear the false state */ optc1_clear_optc_underflow(optc); |