drm/amd/display: Silence type conversion warnings in dml2

[Why]
Compiler build generates type conversion warnings throughout dc/dml2_0
where values are implicitly narrowed (e.g. int/uint32_t/uint64_t assigned
to uint8_t, unsigned char, char, bool, or dml_bool_t), cluttering build
output and masking genuine issues.

[How]
Add explicit casts at each narrowing assignment with ASSERT guards
to catch out-of-range values in debug builds:
- uint8_t: otg_inst, num_planes, pipe_idx, vblank_index fields
- unsigned char: pipe_dlg_param.otg_inst from tg->inst
- char: mcache num_pipes from num_dpps_required
- bool/dml_bool_t: INTERLACE bitfield and fams2 enable flag use != 0
- uint64_t: widen min_hardware_refresh_in_uhz to hold div64_u64 result,
  then cast to unsigned long for min_refresh_uhz with ASSERT

Reviewed-by: Austin Zheng <austin.zheng@amd.com>
Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

3 files changed, 24 insertions, 10 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
index eadf84842ca0..2f0e0048bea8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
@@ -90,7 +90,8 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf
 		struct pipe_ctx *pipe_ctx,
 		struct dml2_context *dml_ctx)
 {
-	unsigned int hblank_start, vblank_start, min_hardware_refresh_in_uhz;
+	unsigned int hblank_start, vblank_start;
+	uint64_t min_hardware_refresh_in_uhz;
 	uint32_t pix_clk_100hz;
 
 	timing->h_active = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe_ctx->dsc_padding_params.dsc_hactive_padding;
@@ -105,7 +106,7 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf
 	timing->h_total = stream->timing.h_total + pipe_ctx->dsc_padding_params.dsc_htotal_padding;
 	timing->v_total = stream->timing.v_total;
 	timing->h_sync_width = stream->timing.h_sync_width;
-	timing->interlaced = stream->timing.flags.INTERLACE;
+	timing->interlaced = (stream->timing.flags.INTERLACE != 0);
 
 	hblank_start = stream->timing.h_total - stream->timing.h_front_porch;
 
@@ -137,7 +138,11 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf
 				(timing->h_total * (long long)calc_max_hardware_v_total(stream)));
 	}
 
-	timing->drr_config.min_refresh_uhz = max(stream->timing.min_refresh_in_uhz, min_hardware_refresh_in_uhz);
+	{
+		uint64_t min_refresh = max((uint64_t)stream->timing.min_refresh_in_uhz, min_hardware_refresh_in_uhz);
+		ASSERT(min_refresh <= ULONG_MAX);
+		timing->drr_config.min_refresh_uhz = (unsigned long)min_refresh;
+	}
 
 	if (dml_ctx->config.callbacks.get_max_flickerless_instant_vtotal_increase &&
 			stream->ctx->dc->config.enable_fpo_flicker_detection == 1)
@@ -697,7 +702,7 @@ unsigned int map_plane_to_dml21_display_cfg(const struct dml2_context *dml_ctx,
 
 	if (!dml21_wrapper_get_plane_id(context, stream_id, plane, &plane_id)) {
 		ASSERT(false);
-		return -1;
+		return UINT_MAX;
 	}
 
 	for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
index ab7ec24268be..4724b08c77e1 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
@@ -420,8 +420,12 @@ static unsigned int dml21_build_fams2_stream_programming_v2(const struct dc *dc,
 			type = static_base_state->stream_v1.base.type;
 
 			/* get information from context */
-			static_base_state->stream_v1.base.num_planes = context->stream_status[dc_stream_idx].plane_count;
-			static_base_state->stream_v1.base.otg_inst = context->stream_status[dc_stream_idx].primary_otg_inst;
+			ASSERT(context->stream_status[dc_stream_idx].plane_count >= 0 &&
+					context->stream_status[dc_stream_idx].plane_count <= 0xFF);
+			ASSERT(context->stream_status[dc_stream_idx].primary_otg_inst >= 0 &&
+					context->stream_status[dc_stream_idx].primary_otg_inst <= 0xFF);
+			static_base_state->stream_v1.base.num_planes = (uint8_t)context->stream_status[dc_stream_idx].plane_count;
+			static_base_state->stream_v1.base.otg_inst = (uint8_t)context->stream_status[dc_stream_idx].primary_otg_inst;
 
 			/* populate pipe masks for planes */
 			for (dc_plane_idx = 0; dc_plane_idx < context->stream_status[dc_stream_idx].plane_count; dc_plane_idx++) {
@@ -458,7 +462,9 @@ static unsigned int dml21_build_fams2_stream_programming_v2(const struct dc *dc,
 			switch (dc->debug.fams_version.minor) {
 			case 1:
 			default:
-				static_sub_state->stream_v1.sub_state.subvp.phantom_otg_inst = phantom_status->primary_otg_inst;
+				ASSERT(phantom_status->primary_otg_inst >= 0 &&
+						phantom_status->primary_otg_inst <= 0xFF);
+				static_sub_state->stream_v1.sub_state.subvp.phantom_otg_inst = (uint8_t)phantom_status->primary_otg_inst;
 
 				/* populate pipe masks for phantom planes */
 				for (dc_plane_idx = 0; dc_plane_idx < phantom_status->plane_count; dc_plane_idx++) {
@@ -516,7 +522,8 @@ void dml21_build_fams2_programming(const struct dc *dc,
 		context->bw_ctx.bw.dcn.fams2_global_config.num_streams = num_fams2_streams;
 	}
 
-	context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable;
+	context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching =
+			(context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable != 0);
 }
 
 bool dml21_is_plane1_enabled(enum dml2_source_format_class source_format)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c
index f3abfdbe6805..cc992af6ac9c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c
@@ -297,7 +297,8 @@ void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context
 		memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor));
 		mcache_config->plane_descriptor = pln_prog->plane_descriptor;
 		mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx];
-		mcache_config->num_pipes = pln_prog->num_dpps_required;
+		ASSERT(pln_prog->num_dpps_required <= 0x7F);
+		mcache_config->num_pipes = (char)pln_prog->num_dpps_required;
 		l->build_mcache_programming_params.num_configurations++;
 
 		if (pln_prog->num_dpps_required == 0) {
@@ -324,7 +325,8 @@ void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context
 			memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor));
 			mcache_config->plane_descriptor = pln_prog->plane_descriptor;
 			mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx];
-			mcache_config->num_pipes = pln_prog->num_dpps_required;
+			ASSERT(pln_prog->num_dpps_required <= 0x7F);
+			mcache_config->num_pipes = (char)pln_prog->num_dpps_required;
 			l->build_mcache_programming_params.num_configurations++;
 
 			for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) {