drm/amd/display: Refactor DCCG into component folder

[why]
cleaning up the code refactor requires dccg to be in its own component.

[how]
move all files under newly created dccg folder and fixing the
makefiles.

Reviewed-by: Martin Leung <martin.leung@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Revalla Hari Krishna <harikrishna.revalla@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

3 files changed, 0 insertions, 170 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
index 435979febb79..fb7471435c69 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
@@ -24,7 +24,6 @@
 #
 
 DCN30 := dcn30_hubp.o \
-	dcn30_dccg.o \
 	dcn30_mpc.o dcn30_vpg.o \
 	dcn30_afmt.o \
 	dcn30_dio_stream_encoder.o \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c
deleted file mode 100644
index d445dfefc047..000000000000
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Copyright 2020 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "reg_helper.h"
-#include "core_types.h"
-#include "dcn30_dccg.h"
-
-#define TO_DCN_DCCG(dccg)\
-	container_of(dccg, struct dcn_dccg, base)
-
-#define REG(reg) \
-	(dccg_dcn->regs->reg)
-
-#undef FN
-#define FN(reg_name, field_name) \
-	dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
-
-#define CTX \
-	dccg_dcn->base.ctx
-#define DC_LOGGER \
-	dccg->ctx->logger
-
-
-static const struct dccg_funcs dccg3_funcs = {
-	.update_dpp_dto = dccg2_update_dpp_dto,
-	.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
-	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
-	.otg_add_pixel = dccg2_otg_add_pixel,
-	.otg_drop_pixel = dccg2_otg_drop_pixel,
-	.dccg_init = dccg2_init
-};
-
-struct dccg *dccg3_create(
-	struct dc_context *ctx,
-	const struct dccg_registers *regs,
-	const struct dccg_shift *dccg_shift,
-	const struct dccg_mask *dccg_mask)
-{
-	struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);
-	struct dccg *base;
-
-	if (dccg_dcn == NULL) {
-		BREAK_TO_DEBUGGER();
-		return NULL;
-	}
-
-	base = &dccg_dcn->base;
-	base->ctx = ctx;
-	base->funcs = &dccg3_funcs;
-
-	dccg_dcn->regs = regs;
-	dccg_dcn->dccg_shift = dccg_shift;
-	dccg_dcn->dccg_mask = dccg_mask;
-
-	return &dccg_dcn->base;
-}
-
-struct dccg *dccg30_create(
-	struct dc_context *ctx,
-	const struct dccg_registers *regs,
-	const struct dccg_shift *dccg_shift,
-	const struct dccg_mask *dccg_mask)
-{
-	struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);
-	struct dccg *base;
-
-	if (dccg_dcn == NULL) {
-		BREAK_TO_DEBUGGER();
-		return NULL;
-	}
-
-	base = &dccg_dcn->base;
-	base->ctx = ctx;
-	base->funcs = &dccg3_funcs;
-
-	dccg_dcn->regs = regs;
-	dccg_dcn->dccg_shift = dccg_shift;
-	dccg_dcn->dccg_mask = dccg_mask;
-
-	return &dccg_dcn->base;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h
deleted file mode 100644
index 3f1da7f3a91c..000000000000
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright 2020 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DCN30_DCCG_H__
-#define __DCN30_DCCG_H__
-
-#include "dcn20/dcn20_dccg.h"
-
-
-#define DCCG_REG_LIST_DCN30() \
-	DCCG_REG_LIST_DCN2(),\
-	DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),\
-	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
-	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
-	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
-	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5),\
-	SR(PHYASYMCLK_CLOCK_CNTL),\
-	SR(PHYBSYMCLK_CLOCK_CNTL),\
-	SR(PHYCSYMCLK_CLOCK_CNTL)
-
-#define DCCG_MASK_SH_LIST_DCN3(mask_sh) \
-	DCCG_MASK_SH_LIST_DCN2(mask_sh),\
-	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\
-	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\
-	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
-	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
-	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
-	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
-	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
-	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
-
-struct dccg *dccg3_create(
-	struct dc_context *ctx,
-	const struct dccg_registers *regs,
-	const struct dccg_shift *dccg_shift,
-	const struct dccg_mask *dccg_mask);
-
-struct dccg *dccg30_create(
-	struct dc_context *ctx,
-	const struct dccg_registers *regs,
-	const struct dccg_shift *dccg_shift,
-	const struct dccg_mask *dccg_mask);
-
-#endif //__DCN30_DCCG_H__