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| author | Alex Deucher <alexander.deucher@amd.com> | 2017-06-15 16:24:01 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 17:21:35 -0400 |
| commit | d4e13b0db124345be93bc2ff39ecb48409da2c9b (patch) | |
| tree | 7069fa7fb33b075b02df025e2d7e1dcd208926d7 /drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | |
| parent | 4e3133c79dc4b7dc0ff81eb884d6cfe736fc49b1 (diff) | |
| download | lwn-d4e13b0db124345be93bc2ff39ecb48409da2c9b.tar.gz lwn-d4e13b0db124345be93bc2ff39ecb48409da2c9b.zip | |
drm/amd/display: decouple per-crtc-plane model
Current design has per-crtc-plane model.
As a result, for asic's that support underlay,
are unable to expose it to user space for modesetting.
To enable this, the drm driver intialisation now runs
for number of surfaces instead of stream/crtc.
This patch plumbs surface capabilities to drm framework
so that it can be effectively used by user space.
Tests: (On Chromium OS for Stoney Only)
* 'modetest -p' now shows additional plane
with YUV capabilities in case of CZ and ST.
* 'plane_test' fails with below error:
[drm:amdgpu_dm_connector_atomic_set_property [amdgpu]] *ERROR* Unsupported screen depth 0
as ther is no support for YUYV
* Checked multimonitor display works fine
Signed-off-by: Shirish S <shirish.s@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 67 |
1 files changed, 51 insertions, 16 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b08ec453b773..d76448d04423 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -49,6 +49,28 @@ #include "modules/inc/mod_freesync.h" +static enum drm_plane_type dm_surfaces_type_default[AMDGPU_MAX_PLANES] = { + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, +}; + +static enum drm_plane_type dm_surfaces_type_carizzo[AMDGPU_MAX_PLANES] = { + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */ +}; + +static enum drm_plane_type dm_surfaces_type_stoney[AMDGPU_MAX_PLANES] = { + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */ +}; + /* * dm_vblank_get_counter * @@ -1051,30 +1073,34 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) uint32_t i; struct amdgpu_connector *aconnector; struct amdgpu_encoder *aencoder; - struct amdgpu_crtc *acrtc; + struct amdgpu_mode_info *mode_info = &adev->mode_info; uint32_t link_cnt; link_cnt = dm->dc->caps.max_links; - if (amdgpu_dm_mode_config_init(dm->adev)) { DRM_ERROR("DM: Failed to initialize mode config\n"); - return -1; + goto fail; } - for (i = 0; i < dm->dc->caps.max_streams; i++) { - acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); - if (!acrtc) - goto fail; + for (i = 0; i < dm->dc->caps.max_surfaces; i++) { + mode_info->planes[i] = kzalloc(sizeof(struct amdgpu_plane), + GFP_KERNEL); + if (!mode_info->planes[i]) { + DRM_ERROR("KMS: Failed to allocate surface\n"); + goto fail_free_planes; + } + mode_info->planes[i]->plane_type = mode_info->plane_type[i]; + if (amdgpu_dm_plane_init(dm, mode_info->planes[i], 1)) { + DRM_ERROR("KMS: Failed to initialize plane\n"); + goto fail_free_planes; + } + } - if (amdgpu_dm_crtc_init( - dm, - acrtc, - i)) { + for (i = 0; i < dm->dc->caps.max_streams; i++) + if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) { DRM_ERROR("KMS: Failed to initialize crtc\n"); - kfree(acrtc); - goto fail; + goto fail_free_planes; } - } dm->display_indexes_num = dm->dc->caps.max_streams; @@ -1125,12 +1151,12 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case CHIP_VEGA10: if (dce110_register_irq_handlers(dm->adev)) { DRM_ERROR("DM: Failed to initialize IRQ\n"); - return -1; + goto fail_free_encoder; } break; default: DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type); - return -1; + goto fail_free_encoder; } drm_mode_config_reset(dm->ddev); @@ -1140,6 +1166,9 @@ fail_free_encoder: kfree(aencoder); fail_free_connector: kfree(aconnector); +fail_free_planes: + for (i = 0; i < dm->dc->caps.max_surfaces; i++) + kfree(mode_info->planes[i]); fail: return -1; } @@ -1361,33 +1390,39 @@ static int dm_early_init(void *handle) adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; + adev->mode_info.plane_type = dm_surfaces_type_default; break; case CHIP_FIJI: case CHIP_TONGA: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 7; + adev->mode_info.plane_type = dm_surfaces_type_default; break; case CHIP_CARRIZO: adev->mode_info.num_crtc = 3; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 9; + adev->mode_info.plane_type = dm_surfaces_type_carizzo; break; case CHIP_STONEY: adev->mode_info.num_crtc = 2; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 9; + adev->mode_info.plane_type = dm_surfaces_type_stoney; break; case CHIP_POLARIS11: case CHIP_POLARIS12: adev->mode_info.num_crtc = 5; adev->mode_info.num_hpd = 5; adev->mode_info.num_dig = 5; + adev->mode_info.plane_type = dm_surfaces_type_default; break; case CHIP_POLARIS10: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; + adev->mode_info.plane_type = dm_surfaces_type_default; break; case CHIP_VEGA10: adev->mode_info.num_crtc = 6; |