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| author | shaoyunl <shaoyun.liu@amd.com> | 2020-04-27 13:38:28 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-05-01 15:19:08 -0400 |
| commit | 43a10b15d44221371126a07347f2b5d11b8314df (patch) | |
| tree | fbfc915eaa3d55e2757290c629d9e1b91c5533c1 /drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | |
| parent | d09f85d52ad6d1da9d6b8aecca6b81e0b4750afb (diff) | |
| download | lwn-43a10b15d44221371126a07347f2b5d11b8314df.tar.gz lwn-43a10b15d44221371126a07347f2b5d11b8314df.zip | |
amd/amdgpu: Limit rlcg write registers only for nv12
Create gfx_v10_0_rlc_funcs_sriov for nv12 with rlcg_write function pointers be initialized
so driver can use RLCG to write aceess CSIB and CP_ME_CNTL registers when nv12 in sriov mode
Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c')
0 files changed, 0 insertions, 0 deletions