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| author | Alex Deucher <alexander.deucher@amd.com> | 2017-09-02 02:01:55 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-03-21 14:24:40 -0500 |
| commit | 2325ff305e44bd061ab7f65c8683bd3fc33f30b2 (patch) | |
| tree | d834cd11866fe856a0603688aab843bcc12281b1 /drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | |
| parent | f79f3fc1412e16ad7bbf18caca5f7c304f822eb6 (diff) | |
| download | lwn-2325ff305e44bd061ab7f65c8683bd3fc33f30b2.tar.gz lwn-2325ff305e44bd061ab7f65c8683bd3fc33f30b2.zip | |
drm/amd/display/dm: add vega12 support
Add support for vega12 to the display manager.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ae512ecb65ee..13a5362d074e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1130,6 +1130,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY; if (adev->asic_type == CHIP_VEGA10 || + adev->asic_type == CHIP_VEGA12 || adev->asic_type == CHIP_RAVEN) client_id = SOC15_IH_CLIENTID_DCE; @@ -1501,6 +1502,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case CHIP_POLARIS10: case CHIP_POLARIS12: case CHIP_VEGA10: + case CHIP_VEGA12: if (dce110_register_irq_handlers(dm->adev)) { DRM_ERROR("DM: Failed to initialize IRQ\n"); goto fail; @@ -1698,6 +1700,7 @@ static int dm_early_init(void *handle) adev->mode_info.plane_type = dm_plane_type_default; break; case CHIP_VEGA10: + case CHIP_VEGA12: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; @@ -1945,6 +1948,7 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); if (adev->asic_type == CHIP_VEGA10 || + adev->asic_type == CHIP_VEGA12 || adev->asic_type == CHIP_RAVEN) { /* Fill GFX9 params */ plane_state->tiling_info.gfx9.num_pipes = |