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| author | pding <Pixel.Ding@amd.com> | 2017-10-12 13:53:20 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-10-19 15:27:18 -0400 |
| commit | e71de0766191d32648cf12dfb2f53f05e52b2dcc (patch) | |
| tree | 1d80f99f733d73191d6052798a62e0999d92bcc4 /drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | |
| parent | f993d628a2d3cb5e0a82a5284b24cef745f42b41 (diff) | |
| download | lwn-e71de0766191d32648cf12dfb2f53f05e52b2dcc.tar.gz lwn-e71de0766191d32648cf12dfb2f53f05e52b2dcc.zip | |
drm/amdgpu: report more amdgpu_fence_info
Only for GFX ring. This can help checking MCBP feature.
The fence at the end of the frame will indicate the completion status.
If the frame completed normally, the fence is written to the address
given in the EVENT_WRITE_EOP packet. If preemption occurred in the
previous IB the address is adjusted by 2 DWs. If work submitted in the
frame was reset before completion, the fence address is adjusted by
four DWs. In the case that preemption occurred, and before preemption
completed a reset was initiated, the address will be adjusted with six
DWs
Signed-off-by: pding <Pixel.Ding@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c')
0 files changed, 0 insertions, 0 deletions