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| author | Andrey Grodzovsky <andrey.grodzovsky@amd.com> | 2019-07-24 11:09:03 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-07-30 23:22:55 -0500 |
| commit | ddcb7fc62f4be99faedfa1764c971a2f31468962 (patch) | |
| tree | c43d94c0b341997249ef2951dde3fed05f87c0c5 /drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | |
| parent | 3d1b8ec76b8f4f91641fd87cc19cd980426a2060 (diff) | |
| download | lwn-ddcb7fc62f4be99faedfa1764c971a2f31468962.tar.gz lwn-ddcb7fc62f4be99faedfa1764c971a2f31468962.zip | |
drm/amdgpu: Add check for USWC support for amdgpu_display_supported_domains
This verifies we don't add GTT as allowed domain for APUs when USWC
is disabled.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_display.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 535650967b1a..ddd8f5b0f2d3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -500,8 +500,15 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev) uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; #if defined(CONFIG_DRM_AMD_DC) + /* + * if amdgpu_bo_validate_uswc returns false it means that USWC mappings + * is not supported for this board. But this mapping is required + * to avoid hang caused by placement of scanout BO in GTT on certain + * APUs. So force the BO placement to VRAM in case this architecture + * will not allow USWC mappings. + */ if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN && - adev->flags & AMD_IS_APU && + adev->flags & AMD_IS_APU && amdgpu_bo_support_uswc(0) && amdgpu_device_asic_has_dc_support(adev->asic_type)) domain |= AMDGPU_GEM_DOMAIN_GTT; #endif |