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| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2016-03-18 14:26:32 +0200 |
|---|---|---|
| committer | Vinod Koul <vinod.koul@intel.com> | 2016-04-04 09:41:43 -0700 |
| commit | 4f4bc0abff79dc9d7ccbd3143adbf8ad1f4fe6ab (patch) | |
| tree | e3a2e86b00b408c281c6d1304228a5c4c9a6111b /drivers/dma/hsu/hsu.h | |
| parent | a197f3c7d48c0c1f45076ea47533a76ba9b1a959 (diff) | |
| download | lwn-4f4bc0abff79dc9d7ccbd3143adbf8ad1f4fe6ab.tar.gz lwn-4f4bc0abff79dc9d7ccbd3143adbf8ad1f4fe6ab.zip | |
dmaengine: hsu: correct use of channel status register
There is a typo in documentation regarding to descriptor empty bit (DESCE)
which is set to 1 when descriptor is empty. Thus, status register at the end of
a transfer usually returns all DESCE bits set and thus it will never be zero.
Moreover, there are 2 bits (CDESC) that encode current descriptor, on which
interrupt has been asserted. In case when we have few descriptors programmed we
might have non-zero value.
Remove DESCE and CDESC bits from DMA channel status register (HSU_CH_SR) when
reading it.
Fixes: 2b49e0c56741 ("dmaengine: append hsu DMA driver")
Cc: stable@vger.kernel.org
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma/hsu/hsu.h')
| -rw-r--r-- | drivers/dma/hsu/hsu.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/dma/hsu/hsu.h b/drivers/dma/hsu/hsu.h index 578a8ee8cd05..6b070c22b1df 100644 --- a/drivers/dma/hsu/hsu.h +++ b/drivers/dma/hsu/hsu.h @@ -41,6 +41,9 @@ #define HSU_CH_SR_DESCTO(x) BIT(8 + (x)) #define HSU_CH_SR_DESCTO_ANY (BIT(11) | BIT(10) | BIT(9) | BIT(8)) #define HSU_CH_SR_CHE BIT(15) +#define HSU_CH_SR_DESCE(x) BIT(16 + (x)) +#define HSU_CH_SR_DESCE_ANY (BIT(19) | BIT(18) | BIT(17) | BIT(16)) +#define HSU_CH_SR_CDESC_ANY (BIT(31) | BIT(30)) /* Bits in HSU_CH_CR */ #define HSU_CH_CR_CHA BIT(0) |