diff options
| author | Stefan Agner <stefan@agner.ch> | 2017-06-08 15:34:47 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-06-19 19:02:41 -0700 |
| commit | 22039d150f716e4e56215d70ad23fb92caa4476e (patch) | |
| tree | 1821f452251a54adf1e15b0827811fc2b4fe230f /drivers/clk/zte | |
| parent | 2a8e44dffb152343ccf2ecd26b8a88f999edfd49 (diff) | |
| download | lwn-22039d150f716e4e56215d70ad23fb92caa4476e.tar.gz lwn-22039d150f716e4e56215d70ad23fb92caa4476e.zip | |
clk: imx7d: create clocks behind rawnand clock gate
The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT
and NAND_CLK_ROOT. However, the gate has been in the chain of the
latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT
only, e.g. as required by APBH-Bridge-DMA.
Add new clocks which represent the clock after the gate, and use a
shared clock gate to correctly model the hardware.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/zte')
0 files changed, 0 insertions, 0 deletions