diff options
| author | Rajeev Kumar <rajeev-dlh.kumar@st.com> | 2012-11-10 12:13:40 +0530 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2012-11-21 11:45:19 -0800 |
| commit | df2449aba4749fb8d04c3c1bbfad5cf8863c323b (patch) | |
| tree | 46b967f34849952fa3c784befddd82875b237fb6 /drivers/clk/spear/spear1310_clock.c | |
| parent | 70ee65771424829fd092a1df9afcc7e24c94004b (diff) | |
| download | lwn-df2449aba4749fb8d04c3c1bbfad5cf8863c323b.tar.gz lwn-df2449aba4749fb8d04c3c1bbfad5cf8863c323b.zip | |
CLK: SPEAr: Fix dev_id & con_id for multiple clocks
dev_id & con_id names of multiple clocks are incorrect. This patch fixes these
names with the names that come via DT.
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Bhavna Yadav <bhavna.yadav@st.com>
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/spear/spear1310_clock.c')
| -rw-r--r-- | drivers/clk/spear/spear1310_clock.c | 30 |
1 files changed, 16 insertions, 14 deletions
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c index 0fcec2aae19c..f13b1d23b4a9 100644 --- a/drivers/clk/spear/spear1310_clock.c +++ b/drivers/clk/spear/spear1310_clock.c @@ -401,7 +401,7 @@ void __init spear1310_clk_init(void) clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "fc900000.rtc"); + clk_register_clkdev(clk, NULL, "e0580000.rtc"); /* clock derived from 24 or 25 MHz osc clk */ /* vco-pll */ @@ -615,7 +615,7 @@ void __init spear1310_clk_init(void) ARRAY_SIZE(gmac_phy_parents), 0, SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT, SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock); - clk_register_clkdev(clk, NULL, "stmmacphy.0"); + clk_register_clkdev(clk, "stmmacphy.0", NULL); /* clcd */ clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents, @@ -638,7 +638,7 @@ void __init spear1310_clk_init(void) clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, "clcd_clk", NULL); + clk_register_clkdev(clk, NULL, "e1000000.clcd"); /* i2s */ clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents, @@ -705,35 +705,37 @@ void __init spear1310_clk_init(void) clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, "usbh.0_clk", NULL); + clk_register_clkdev(clk, NULL, "e4000000.ohci"); + clk_register_clkdev(clk, NULL, "e4800000.ehci"); clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, "usbh.1_clk", NULL); + clk_register_clkdev(clk, NULL, "e5000000.ohci"); + clk_register_clkdev(clk, NULL, "e5800000.ehci"); clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "uoc"); + clk_register_clkdev(clk, NULL, "e3800000.otg"); clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "dw_pcie.0"); - clk_register_clkdev(clk, NULL, "ahci.0"); + clk_register_clkdev(clk, NULL, "b1000000.ahci"); clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "dw_pcie.1"); - clk_register_clkdev(clk, NULL, "ahci.1"); + clk_register_clkdev(clk, NULL, "b1800000.ahci"); clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "dw_pcie.2"); - clk_register_clkdev(clk, NULL, "ahci.2"); + clk_register_clkdev(clk, NULL, "b4000000.ahci"); clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0, @@ -754,7 +756,7 @@ void __init spear1310_clk_init(void) clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_ADC_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "adc_clk"); + clk_register_clkdev(clk, NULL, "e0080000.adc"); /* clock derived from apb clk */ clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, @@ -916,15 +918,15 @@ void __init spear1310_clk_init(void) SPEAR1310_RAS_CTRL_REG1, SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT, SPEAR1310_PHY_CLK_MASK, 0, &_lock); - clk_register_clkdev(clk, NULL, "stmmacphy.1"); - clk_register_clkdev(clk, NULL, "stmmacphy.2"); - clk_register_clkdev(clk, NULL, "stmmacphy.4"); + clk_register_clkdev(clk, "stmmacphy.1", NULL); + clk_register_clkdev(clk, "stmmacphy.2", NULL); + clk_register_clkdev(clk, "stmmacphy.4", NULL); clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents, ARRAY_SIZE(rmii_phy_parents), 0, SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT, SPEAR1310_PHY_CLK_MASK, 0, &_lock); - clk_register_clkdev(clk, NULL, "stmmacphy.3"); + clk_register_clkdev(clk, "stmmacphy.3", NULL); clk = clk_register_mux(NULL, "uart1_mclk", uart_parents, ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, |