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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-07-19 16:30:45 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-08-16 09:51:47 +0200 |
| commit | 09a7dea9d58aadda90af5ad4dce1d540fe830868 (patch) | |
| tree | c2fa6faccf64d6e758746ca6a5086962986515d1 /drivers/clk/renesas/rcar-gen3-cpg.c | |
| parent | 714c53aa2e2d6d60ca1e7d18980767c8b715c288 (diff) | |
| download | lwn-09a7dea9d58aadda90af5ad4dce1d540fe830868.tar.gz lwn-09a7dea9d58aadda90af5ad4dce1d540fe830868.zip | |
clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3
On some R-Car Gen3 SoCs (e.g. R-Car D3), PLL1 and PLL3 use a divider
value different from one. Extend struct rcar_gen3_cpg_pll_config to handle
this. As all multipliers and dividers are small, table size increase
can be kept limited by storing them in u8s instead of unsigned ints,
which saves ca. 0.5 KiB for a generic kernel.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/renesas/rcar-gen3-cpg.c')
| -rw-r--r-- | drivers/clk/renesas/rcar-gen3-cpg.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index d4d27cf6110d..3f922fea9671 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -296,6 +296,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, case CLK_TYPE_GEN3_PLL1: mult = cpg_pll_config->pll1_mult; + div = cpg_pll_config->pll1_div; break; case CLK_TYPE_GEN3_PLL2: @@ -313,6 +314,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, case CLK_TYPE_GEN3_PLL3: mult = cpg_pll_config->pll3_mult; + div = cpg_pll_config->pll3_div; break; case CLK_TYPE_GEN3_PLL4: |