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| author | Tomeu Vizoso <tomeu.vizoso@collabora.com> | 2015-01-23 12:03:31 +0100 |
|---|---|---|
| committer | Michael Turquette <mturquette@linaro.org> | 2015-02-02 14:23:42 -0800 |
| commit | 1c8e600440c7f5036bd9a94526d01e9c7cb68dca (patch) | |
| tree | 36c9811e976332bc23a00a6fb216dce5e6b55a5a /drivers/clk/qcom/clk-pll.c | |
| parent | b09d6d99102504a929cfaba4cd0e07658d7f01d1 (diff) | |
| download | lwn-1c8e600440c7f5036bd9a94526d01e9c7cb68dca.tar.gz lwn-1c8e600440c7f5036bd9a94526d01e9c7cb68dca.zip | |
clk: Add rate constraints to clocks
Adds a way for clock consumers to set maximum and minimum rates. This
can be used for thermal drivers to set minimum rates, or by misc.
drivers to set maximum rates to assure a minimum performance level.
Changes the signature of the determine_rate callback by adding the
parameters min_rate and max_rate.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[sboyd@codeaurora.org: set req_rate in __clk_init]
Signed-off-by: Michael Turquette <mturquette@linaro.org>
[mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate
migrated clk-private.h changes to clk.c]
Diffstat (limited to 'drivers/clk/qcom/clk-pll.c')
| -rw-r--r-- | drivers/clk/qcom/clk-pll.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/qcom/clk-pll.c b/drivers/clk/qcom/clk-pll.c index 60873a7f45d9..b4325f65a1bf 100644 --- a/drivers/clk/qcom/clk-pll.c +++ b/drivers/clk/qcom/clk-pll.c @@ -141,6 +141,7 @@ struct pll_freq_tbl *find_freq(const struct pll_freq_tbl *f, unsigned long rate) static long clk_pll_determine_rate(struct clk_hw *hw, unsigned long rate, + unsigned long min_rate, unsigned long max_rate, unsigned long *p_rate, struct clk_hw **p) { struct clk_pll *pll = to_clk_pll(hw); |