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authorSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>2021-01-20 07:50:02 -0600
committerJoerg Roedel <jroedel@suse.de>2021-01-28 11:57:08 +0100
commita44092e326d403c7878018ba532369f84d31dbfa (patch)
tree8b62aeb66ef956553aeb4667d5777b4787a228e0 /crypto/adiantum.c
parent6ee1d745b7c9fd573fba142a2efdad76a9f1cb04 (diff)
downloadlwn-a44092e326d403c7878018ba532369f84d31dbfa.tar.gz
lwn-a44092e326d403c7878018ba532369f84d31dbfa.zip
iommu/amd: Use IVHD EFR for early initialization of IOMMU features
IOMMU Extended Feature Register (EFR) is used to communicate the supported features for each IOMMU to the IOMMU driver. This is normally read from the PCI MMIO register offset 0x30, and used by the iommu_feature() helper function. However, there are certain scenarios where the information is needed prior to PCI initialization, and the iommu_feature() function is used prematurely w/o warning. This has caused incorrect initialization of IOMMU. This is the case for the commit 6d39bdee238f ("iommu/amd: Enforce 4k mapping for certain IOMMU data structures") Since, the EFR is also available in the IVHD header, and is available to the driver prior to PCI initialization. Therefore, default to using the IVHD EFR instead. Fixes: 6d39bdee238f ("iommu/amd: Enforce 4k mapping for certain IOMMU data structures") Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Tested-by: Brijesh Singh <brijesh.singh@amd.com> Reviewed-by: Robert Richter <rrichter@amd.com> Link: https://lore.kernel.org/r/20210120135002.2682-1-suravee.suthikulpanit@amd.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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