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| author | Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> | 2024-05-27 15:55:36 +0300 |
|---|---|---|
| committer | Borislav Petkov (AMD) <bp@alien8.de> | 2024-06-24 19:19:55 +0200 |
| commit | 724852059e97c48557151b3aa4af424614819752 (patch) | |
| tree | b952cdb86074026b0406b060a26796e74f49a34e /arch/x86/pci | |
| parent | ec0b4c4d45cf7cf9a6c9626a494a89cb1ae7c645 (diff) | |
| download | lwn-724852059e97c48557151b3aa4af424614819752.tar.gz lwn-724852059e97c48557151b3aa4af424614819752.zip | |
x86/pci/intel_mid_pci: Fix PCIBIOS_* return code handling
intel_mid_pci_irq_enable() uses pci_read_config_byte() that returns
PCIBIOS_* codes. The error handling, however, assumes the codes are
normal errnos because it checks for < 0.
intel_mid_pci_irq_enable() also returns the PCIBIOS_* code back to the
caller but the function is used as the (*pcibios_enable_irq) function
which should return normal errnos.
Convert the error check to plain non-zero check which works for
PCIBIOS_* return codes and convert the PCIBIOS_* return code using
pcibios_err_to_errno() into normal errno before returning it.
Fixes: 5b395e2be6c4 ("x86/platform/intel-mid: Make IRQ allocation a bit more flexible")
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20240527125538.13620-2-ilpo.jarvinen@linux.intel.com
Diffstat (limited to 'arch/x86/pci')
| -rw-r--r-- | arch/x86/pci/intel_mid_pci.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c index 8edd62206604..722a33be08a1 100644 --- a/arch/x86/pci/intel_mid_pci.c +++ b/arch/x86/pci/intel_mid_pci.c @@ -233,9 +233,9 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev) return 0; ret = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi); - if (ret < 0) { + if (ret) { dev_warn(&dev->dev, "Failed to read interrupt line: %d\n", ret); - return ret; + return pcibios_err_to_errno(ret); } id = x86_match_cpu(intel_mid_cpu_ids); |